noncpu - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	Move the core logic out of the top module.	Julian Blake Kongslie	2021-04-18	2	-219/+232
*	Change synthesis of PLL wrapper to avoid latch logic.pre-dp-8	Julian Blake Kongslie	2021-04-15	2	-32/+20
*	Use internal PLL for clock and reset generation.	Julian Blake Kongslie	2021-04-14	2	-6/+154
*	Add UART receive opbit.	Julian Blake Kongslie	2021-04-07	1	-0/+12
*	Switch back to $past-based scheduling; my clever idea wasn't clever enough.	Julian Blake Kongslie	2021-04-07	4	-101/+74
*	Change the null byte from no-op to halt.	Julian Blake Kongslie	2021-04-05	1	-1/+1
*	Change our simulator timing model to use continuous assignment guards.	Julian Blake Kongslie	2021-04-05	4	-86/+113
*	Make PC ADDR-sized rather than DATA-sized for now	Julian Blake Kongslie	2021-04-05	1	-3/+3
*	Remove some old debug messages.	Julian Blake Kongslie	2021-04-05	1	-11/+1
*	Remove idx, add indirect jumps, renumber opcodes so NOP=0, add absolute label...	Julian Blake Kongslie	2021-04-04	1	-31/+34
*	Add indirect memory operations.	Julian Blake Kongslie	2021-04-04	1	-6/+30
*	Very fancy improved Fibonacci machine, with HDL convert-to-ASCII functionality	Julian Blake Kongslie	2021-04-04	1	-0/+11
*	Add a Fibonacci sequence to the end of output (no ASCII conversion yet)	Julian Blake Kongslie	2021-03-29	1	-1/+1
*	Convert to using $sampled instead of $past, for more uniformity.	Julian Blake Kongslie	2021-03-29	3	-13/+9
*	Fix WIDTH warnings from verilator.	Julian Blake Kongslie	2021-03-29	1	-5/+8
*	Possibly slightly less lame.	Julian Blake Kongslie	2021-03-28	1	-10/+10
*	Yet another lame attempt.	Julian Blake Kongslie	2021-03-28	2	-34/+71
*	Pessimize JTAG UART somewhat.	Julian Blake Kongslie	2021-03-28	2	-8/+5
*	Use a separate memory module.	Julian Blake Kongslie	2021-03-28	2	-9/+110
*	Some more interesting opcodes.	Julian Blake Kongslie	2021-03-28	1	-8/+23
*	Initial commit.	Julian Blake Kongslie	2021-03-28	3	-0/+178