noncpu - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Keyboard input.	Julian Blake Kongslie	2021-05-09	1	-2/+25
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*	Add a bunch of microcoded instructions.	Julian Blake Kongslie	2021-05-02	1	-3/+90
\| \| \| \|	This is a minimum viable PDP-8 that can print "Hello, world!" and halt.
*	Fix a few trivial errors with vector sizes, state names, and syntax.	Julian Blake Kongslie	2021-04-18	1	-4/+4
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*	PDP-8 memory opcodes	Julian Blake Kongslie	2021-04-18	1	-84/+92
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*	Move the core logic out of the top module.	Julian Blake Kongslie	2021-04-18	2	-219/+232
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*	Change synthesis of PLL wrapper to avoid latch logic.pre-dp-8	Julian Blake Kongslie	2021-04-15	2	-32/+20
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*	Use internal PLL for clock and reset generation.	Julian Blake Kongslie	2021-04-14	2	-6/+154
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*	Add UART receive opbit.	Julian Blake Kongslie	2021-04-07	1	-0/+12
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*	Switch back to $past-based scheduling; my clever idea wasn't clever enough.	Julian Blake Kongslie	2021-04-07	4	-101/+74
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*	Change the null byte from no-op to halt.	Julian Blake Kongslie	2021-04-05	1	-1/+1
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*	Change our simulator timing model to use continuous assignment guards.	Julian Blake Kongslie	2021-04-05	4	-86/+113
\| \| \| \| \| \| \|	Instead of depending on verilator getting $past right, this (ab-)uses the SystemVerilog scheduling model which allows us to get a consistent view of the universe by "isolating" the blocking updates. Easier to code to and seems to be more reliable in verilator.
*	Make PC ADDR-sized rather than DATA-sized for now	Julian Blake Kongslie	2021-04-05	1	-3/+3
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*	Remove some old debug messages.	Julian Blake Kongslie	2021-04-05	1	-11/+1
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*	Remove idx, add indirect jumps, renumber opcodes so NOP=0, add absolute ↵	Julian Blake Kongslie	2021-04-04	1	-31/+34
\| \| \| \|	labels to asm.rb
*	Add indirect memory operations.	Julian Blake Kongslie	2021-04-04	1	-6/+30
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*	Very fancy improved Fibonacci machine, with HDL convert-to-ASCII functionality	Julian Blake Kongslie	2021-04-04	1	-0/+11
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*	Add a Fibonacci sequence to the end of output (no ASCII conversion yet)	Julian Blake Kongslie	2021-03-29	1	-1/+1
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*	Convert to using $sampled instead of $past, for more uniformity.	Julian Blake Kongslie	2021-03-29	3	-13/+9
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*	Fix WIDTH warnings from verilator.	Julian Blake Kongslie	2021-03-29	1	-5/+8
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*	Possibly slightly less lame.	Julian Blake Kongslie	2021-03-28	1	-10/+10
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*	Yet another lame attempt.	Julian Blake Kongslie	2021-03-28	2	-34/+71
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*	Pessimize JTAG UART somewhat.	Julian Blake Kongslie	2021-03-28	2	-8/+5
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*	Use a separate memory module.	Julian Blake Kongslie	2021-03-28	2	-9/+110
\| \| \| \|	Hopefully this will infer a memory the way we want in Quartus.
*	Some more interesting opcodes.	Julian Blake Kongslie	2021-03-28	1	-8/+23
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*	Initial commit.	Julian Blake Kongslie	2021-03-28	3	-0/+178