From 15daf2fe9fd13e18609b2141c3346fec6389bda9 Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Sun, 24 Oct 2021 15:02:31 -0700 Subject: More blinkenlights work. --- PLAN | 17 +++++++++ hdl/core.sv | 73 +++++++++++++++++++++++++++++++++++--- hdl/panel.sv | 8 +++++ hdl/top.sv | 112 +++++++++++++++++++++++++++++++++++++++++++++------------- mem/hello.pal | 2 +- 5 files changed, 183 insertions(+), 29 deletions(-) diff --git a/PLAN b/PLAN index d5c2311..ffc0ba1 100644 --- a/PLAN +++ b/PLAN @@ -1,3 +1,20 @@ +Turn on blinkenlights from the PDP core + +There's probably a bug in the UART TX code that's dropping characters when it gets full + +Debounce switches + +Implement switch features: + Start + Load_Add + Deposit + Examine + Continue + Stop + Single_Step + Single_Inst + The DF* IF* and SR* data switches + Don't ignore 6000 and 6001 Add "interrupts enabled" flag diff --git a/hdl/core.sv b/hdl/core.sv index 1b61944..c0e1a63 100644 --- a/hdl/core.sv +++ b/hdl/core.sv @@ -6,21 +6,58 @@ module core ) ( input bit clk , input bit reset + + , input bit switch_cont + + , output bit [0:ADDR_BITS-1] led_pc + , output bit [0:ADDR_BITS-1] led_memaddr + , output bit [0:DATA_BITS-1] led_memdata + , output bit [0:DATA_BITS-1] led_acc + , output bit [0:DATA_BITS-1] led_mq + , output bit led_and + , output bit led_tad + , output bit led_isz + , output bit led_dca + , output bit led_jms + , output bit led_jmp + , output bit led_iot + , output bit led_opr + , output bit led_fetch + , output bit led_execute + , output bit led_defer + , output bit led_word_count + , output bit led_current_address + , output bit led_break + , output bit led_ion + , output bit led_pause + , output bit led_run + , output bit [0:4] led_step_counter + , output bit [0:2] led_df + , output bit [0:2] led_if + , output bit led_link ); +bit run; +assign led_run = run; + bit mem_ready; bit mem_valid; bit mem_write; bit [ADDR_BITS-1:0] mem_address; bit [DATA_BITS-1:0] mem_write_data; +assign led_df = 0; +assign led_if = 0; +assign led_memaddr = mem_address; + bit mem_read_valid; bit [DATA_BITS-1:0] mem_read_data; mem #( .ADDR_BITS(ADDR_BITS) , .DATA_BITS(DATA_BITS) - , .INIT_FILE("mem/focal69.loaded.hex") +// , .INIT_FILE("mem/focal69.loaded.hex") + , .INIT_FILE("build/mem/hello.hex") ) memory ( .clk(clk) @@ -67,6 +104,19 @@ bit [8:0] operand; bit [DATA_BITS-1:0] acc; bit link; +assign led_pc = pc; +assign led_acc = acc; +assign led_link = link; + +assign led_and = opcode == 0; +assign led_tad = opcode == 1; +assign led_isz = opcode == 2; +assign led_dca = opcode == 3; +assign led_jms = opcode == 4; +assign led_jmp = opcode == 5; +assign led_iot = opcode == 6; +assign led_opr = opcode == 7; + bit kbd_valid; bit [DATA_BITS-1:0] kbd_data; @@ -87,8 +137,14 @@ enum , HALT } state; +assign led_fetch = state == FETCH || state == DECODE; +assign led_execute = state == AGEN || state == EXEC; +assign led_defer = state == INDIRECT || state == INDIRECTED || state == PREINC; +assign led_pause = state == MEMWAIT || state == HALT; + always_ff @(posedge clk) begin if (reset) begin + run = 0; mem_valid = 0; rx_ready = 0; tx_valid = 0; @@ -98,7 +154,9 @@ always_ff @(posedge clk) begin link = 1; kbd_valid = 0; state = state.first; - end else begin + end else if (run || switch_cont) begin + run = 1; + if (`lag(tx_ready)) tx_valid = 0; if (rx_ready && `lag(rx_valid)) begin kbd_valid = 1; @@ -122,6 +180,7 @@ always_ff @(posedge clk) begin mem_write = 0; if (`lag(mem_read_valid)) begin state = FETCH; + led_memdata = `lag(mem_read_data); {opcode, operand} = `lag(mem_read_data); // $display("%o: decode %o %o", pc-1, opcode, operand); // verilator lint_off WIDTH @@ -261,10 +320,12 @@ always_ff @(posedge clk) begin end if (`lag(mem_read_valid)) begin if (address[7:3] == 5'b00001) begin + led_memdata = `lag(mem_read_data); address = {{(ADDR_BITS - DATA_BITS){1'b0}}, `lag(mem_read_data)}; address += 1; state = PREINC; end else begin + led_memdata = `lag(mem_read_data); address = {{(ADDR_BITS - DATA_BITS){1'b0}}, `lag(mem_read_data)}; case (opcode) 'o0, 'o1, 'o2: state = AGEN; @@ -282,6 +343,7 @@ always_ff @(posedge clk) begin mem_valid = 1; mem_write = 1; mem_write_data = address[DATA_BITS-1:0]; + led_memdata = mem_write_data; case (opcode) 'o0, 'o1, 'o2: state = `lag(mem_ready) ? AGEN : PREINC; 'o3, 'o4, 'o5: state = `lag(mem_ready) ? EXEC : PREINC; @@ -311,13 +373,14 @@ always_ff @(posedge clk) begin if (! stall) begin state = FETCH; case (opcode) - 'o0: acc &= `lag(mem_read_data); - 'o1: {link, acc} += {1'b0, `lag(mem_read_data)}; + 'o0: begin led_memdata = `lag(mem_read_data); acc &= `lag(mem_read_data); end + 'o1: begin led_memdata = `lag(mem_read_data); {link, acc} += {1'b0, `lag(mem_read_data)}; end 'o2: begin mem_valid = 1; mem_address = address; mem_write = 1; mem_write_data = `lag(mem_read_data) + 1; + led_memdata = mem_write_data; if (mem_write_data == 0) ++pc; state = MEMWAIT; end @@ -326,6 +389,7 @@ always_ff @(posedge clk) begin mem_address = address; mem_write = 1; mem_write_data = acc; + led_memdata = mem_write_data; acc = 0; state = MEMWAIT; end @@ -334,6 +398,7 @@ always_ff @(posedge clk) begin mem_address = address; mem_write = 1; mem_write_data = pc[DATA_BITS-1:0]; + led_memdata = mem_write_data; pc = address + 1; state = MEMWAIT; end diff --git a/hdl/panel.sv b/hdl/panel.sv index fc1f718..5d47484 100644 --- a/hdl/panel.sv +++ b/hdl/panel.sv @@ -14,13 +14,21 @@ module panel enum { LED_ROW1 + , DEAD_ROW2 , LED_ROW2 + , DEAD_ROW3 , LED_ROW3 + , DEAD_ROW4 , LED_ROW4 + , DEAD_ROW5 , LED_ROW5 + , DEAD_ROW6 , LED_ROW6 + , DEAD_ROW7 , LED_ROW7 + , DEAD_ROW8 , LED_ROW8 + , DEAD_ROW9 , SWITCH_PREP , SWITCH_ROW1 , SWITCH_ROW2 diff --git a/hdl/top.sv b/hdl/top.sv index abd6f30..4af7ad4 100644 --- a/hdl/top.sv +++ b/hdl/top.sv @@ -12,7 +12,7 @@ module top bit clk; bit reset; -clock +clock // 45 MHz #( .MULTIPLY_BY(9) , .DIVIDE_BY(10) ) pll @@ -24,9 +24,9 @@ clock bit slowclk; bit slowreset; -clock +clock // 100 kHz #( .MULTIPLY_BY(1) - , .DIVIDE_BY(5000) + , .DIVIDE_BY(500) ) slowpll ( .native_clk(native_clk) , .reset_n(reset_n) @@ -49,34 +49,98 @@ panel fp , .gpioc(gpioc) ); -assign led[1] = switch[1]; -assign led[2] = switch[2]; -assign led[3] = switch[3]; -assign led[4] = 0; -assign led[5] = 0; -assign led[6] = 0; -assign led[7] = 0; -assign led[8] = 0; +bit [3:1] switch_df; +bit [3:1] switch_if; +bit [12:1] switch_sr; +bit switch_start; +bit switch_load_add; +bit switch_dep; +bit switch_exam; +bit switch_cont; +bit switch_stop; +bit switch_sing_step; +bit switch_sing_inst; -/* -wire [7:0] debugchar; -assign debugchar = "0" + {switch[1][1], switch[1][2], switch[3][1]}; +assign switch_df = switch[2][3:1]; +assign switch_if = switch[2][6:4]; +assign switch_sr = switch[1]; +assign switch_start = switch[3][1]; +assign switch_load_add = switch[3][2]; +assign switch_dep = switch[3][3]; +assign switch_exam = switch[3][4]; +assign switch_cont = switch[3][5]; +assign switch_stop = switch[3][6]; +assign switch_sing_step = switch[3][7]; +assign switch_sing_inst = switch[3][8]; -jtag_uart debug - ( .clk(slowclk) - , .reset(slowreset) +bit [11:0] led_pc; +bit [11:0] led_memaddr; +bit [11:0] led_memdata; +bit [11:0] led_acc; +bit [11:0] led_mq; +bit led_and; +bit led_tad; +bit led_isz; +bit led_dca; +bit led_jms; +bit led_jmp; +bit led_iot; +bit led_opr; +bit led_fetch; +bit led_execute; +bit led_defer; +bit led_word_count; +bit led_current_address; +bit led_break; +bit led_ion; +bit led_pause; +bit led_run; +bit [4:0] led_step_counter; +bit [2:0] led_df; +bit [2:0] led_if; +bit led_link; - , .rx_ready(0) - , .tx_valid(1) - , .tx_data(debugchar) - ); -*/ +assign led[1] = {led_pc[0], led_pc[1], led_pc[2], led_pc[3], led_pc[4], led_pc[5], led_pc[6], led_pc[7], led_pc[8], led_pc[9], led_pc[10], led_pc[11]}; +assign led[2] = {led_memaddr[0], led_memaddr[1], led_memaddr[2], led_memaddr[3], led_memaddr[4], led_memaddr[5], led_memaddr[6], led_memaddr[7], led_memaddr[8], led_memaddr[9], led_memaddr[10], led_memaddr[11]}; +assign led[3] = {led_memdata[0], led_memdata[1], led_memdata[2], led_memdata[3], led_memdata[4], led_memdata[5], led_memdata[6], led_memdata[7], led_memdata[8], led_memdata[9], led_memdata[10], led_memdata[11]}; +assign led[4] = {led_acc[0], led_acc[1], led_acc[2], led_acc[3], led_acc[4], led_acc[5], led_acc[6], led_acc[7], led_acc[8], led_acc[9], led_acc[10], led_acc[11]}; +assign led[5] = {led_mq[0], led_mq[1], led_mq[2], led_mq[3], led_mq[4], led_mq[5], led_mq[6], led_mq[7], led_mq[8], led_mq[9], led_mq[10], led_mq[11]}; +assign led[6] = {led_word_count, led_defer, led_execute, led_fetch, led_opr, led_iot, led_jmp, led_jms, led_dca, led_isz, led_tad, led_and}; +assign led[7] = {led_step_counter, led_run, led_pause, led_ion, led_break, led_current_address}; +assign led[8] = {led_link, led_if, led_df}; -/* core cpu ( .clk(clk) , .reset(reset) + + , .switch_cont(switch_cont) + + , .led_pc(led_pc) + , .led_memaddr(led_memaddr) + , .led_memdata(led_memdata) + , .led_acc(led_acc) + , .led_mq(led_mq) + , .led_and(led_and) + , .led_tad(led_tad) + , .led_isz(led_isz) + , .led_dca(led_dca) + , .led_jms(led_jms) + , .led_jmp(led_jmp) + , .led_iot(led_iot) + , .led_opr(led_opr) + , .led_fetch(led_fetch) + , .led_execute(led_execute) + , .led_defer(led_defer) + , .led_word_count(led_word_count) + , .led_current_address(led_current_address) + , .led_break(led_break) + , .led_ion(led_ion) + , .led_pause(led_pause) + , .led_run(led_run) + , .led_step_counter(led_step_counter) + , .led_df(led_df) + , .led_if(led_if) + , .led_link(led_link) ); -*/ endmodule diff --git a/mem/hello.pal b/mem/hello.pal index 989eff8..ef93f87 100644 --- a/mem/hello.pal +++ b/mem/hello.pal @@ -7,7 +7,7 @@ LOOP, TAD I 10 JMP ECHO TLS TSF - JMP .-1 + JMP START CLA JMP LOOP ECHO, KSF -- cgit v1.2.3