From 238a43e587bfbe6574d34ef36553619249797260 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Wed, 7 Apr 2021 17:02:03 -0700
Subject: Switch back to $past-based scheduling; my clever idea wasn't clever
 enough.

---
 hdl/jtag_uart.sv |  37 ++++++++------------
 hdl/mem.sv       |  26 +++++---------
 hdl/top.sv       | 105 ++++++++++++++++++++++++-------------------------------
 hdl/util.svh     |   7 ++--
 4 files changed, 74 insertions(+), 101 deletions(-)

diff --git a/hdl/jtag_uart.sv b/hdl/jtag_uart.sv
index 2b5f334..096b1c9 100644
--- a/hdl/jtag_uart.sv
+++ b/hdl/jtag_uart.sv
@@ -18,13 +18,6 @@ module jtag_uart
     ,   input   bit [7:0]   tx_data
     );
 
-`input(rx_ready)
-`output(rx_valid)
-`output(rx_data)
-`output(tx_ready)
-`input(tx_valid)
-`input(tx_data)
-
 `ifdef SYNTHESIS
 
 alt_jtag_atlantic
@@ -35,12 +28,12 @@ alt_jtag_atlantic
     ) real_jtag
     (   .clk(clk)
     ,   .rst_n(!reset)
-    ,   .r_dat(tx_data_)
-    ,   .r_val(tx_valid_)
-    ,   .r_ena(tx_ready_)
-    ,   .t_dat(rx_data_)
-    ,   .t_dav(rx_ready_)
-    ,   .t_ena(rx_valid_)
+    ,   .r_dat(tx_data)
+    ,   .r_val(tx_valid)
+    ,   .r_ena(tx_ready)
+    ,   .t_dat(rx_data)
+    ,   .t_dav(rx_ready)
+    ,   .t_ena(rx_valid)
     );
 
 `else
@@ -55,34 +48,34 @@ bit [7:0] tx_b_data;
 
 always_ff @(posedge clk) begin
     if (reset) begin
-        rx_valid_ = 0;
-        tx_ready_ = 0;
+        rx_valid = 0;
+        tx_ready = 0;
         sim_rx_addr = 0;
         tx_b_valid = 0;
     end else begin
         automatic bit [7:0] sim_rx_data = sim_rx_rom[sim_rx_addr];
 
         // RX logic
-        if (rx_ready_) rx_valid_ = 0;
-        if (!rx_valid_ && (sim_rx_data != 0)) begin
+        if (`lag(rx_ready)) rx_valid = 0;
+        if (!rx_valid && (sim_rx_data != 0)) begin
 `ifdef JTAG_UART_LOCAL_ECHO
             $write("%s", sim_rx_data);
 `endif
-            rx_valid_ = 1;
-            rx_data_ = sim_rx_data;
+            rx_valid = 1;
+            rx_data = sim_rx_data;
             ++sim_rx_addr;
         end
 
         // TX logic
-        if (tx_ready_ && tx_valid_) begin
+        if (tx_ready && `lag(tx_valid)) begin
             tx_b_valid = 1;
-            tx_b_data = tx_data_;
+            tx_b_data = `lag(tx_data);
         end
         if (tx_b_valid) begin
             $write("%s", tx_b_data);
             tx_b_valid = 0;
         end
-        tx_ready_ = !tx_b_valid;
+        tx_ready = !tx_b_valid;
     end
 end
 
diff --git a/hdl/mem.sv b/hdl/mem.sv
index c362e37..9c5f567 100644
--- a/hdl/mem.sv
+++ b/hdl/mem.sv
@@ -18,32 +18,24 @@ parameter ADDR_BITS;
 parameter DATA_BITS;
 parameter INIT_FILE;
 
-`output(ready)
-`input(valid)
-`input(write)
-`input(address)
-`input(write_data)
-`output(read_valid)
-`output(read_data)
-
 bit [DATA_BITS-1:0] storage [0:(1<<ADDR_BITS)-1];
 initial $readmemh(INIT_FILE, storage);
 
 always_ff @(posedge clk) begin
     if (reset) begin
-        ready_ = 0;
-        read_valid_ = 0;
+        ready = 0;
+        read_valid = 0;
     end else begin
-        read_valid_ = 0;
-        if (ready_ && valid_) begin
-            if (write_) begin
-                storage[address_] = write_data_;
+        read_valid = 0;
+        if (ready && `lag(valid)) begin
+            if (`lag(write)) begin
+                storage[`lag(address)] = `lag(write_data);
             end else begin
-                read_valid_ = 1;
-                read_data_ = storage[address_];
+                read_valid = 1;
+                read_data = storage[`lag(address)];
             end
         end
-        ready_ = 1;
+        ready = 1;
     end
 end
 
diff --git a/hdl/top.sv b/hdl/top.sv
index a1cdbf7..3cda157 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -41,14 +41,6 @@ mem
     ,   .read_data(mem_read_data)
     );
 
-`input(mem_ready)
-`output(mem_valid)
-`output(mem_address)
-`output(mem_write)
-`output(mem_write_data)
-`input(mem_read_valid)
-`input(mem_read_data)
-
 bit rx_ready;
 bit rx_valid;
 bit [7:0] rx_data;
@@ -72,13 +64,6 @@ jtag_uart
     ,   .tx_data(tx_data)
     );
 
-`output(rx_ready)
-`input(rx_valid)
-`input(rx_data)
-`input(tx_ready)
-`output(tx_valid)
-`output(tx_data)
-
 bit [ADDR_BITS-1:0] pc;
 bit [3:0] opcode;
 bit [7:0] operand;
@@ -99,33 +84,33 @@ enum
 
 always_ff @(posedge clk) begin
     if (reset) begin
-        mem_valid_ = 0;
-        rx_ready_ = 0;
-        tx_valid_ = 0;
-        tx_data_ = 0;
+        mem_valid = 0;
+        rx_ready = 0;
+        tx_valid = 0;
+        tx_data = 0;
         pc = 0;
         acc = 0;
         state = state.first;
     end else begin
-        if (tx_ready_) tx_valid_ = 0;
+        if (`lag(tx_ready)) tx_valid = 0;
 
         case (state)
             FETCH: begin
-                mem_valid_ = 1;
-                mem_address_ = pc;
-                mem_write_ = 0;
-                if (mem_ready_) begin
+                mem_valid = 1;
+                mem_address = pc;
+                mem_write = 0;
+                if (`lag(mem_ready)) begin
                     state = DECODE;
                     ++pc;
                 end
             end
 
             DECODE: begin
-                mem_valid_ = 0;
-                mem_write_ = 0;
-                if (mem_read_valid_) begin
+                mem_valid = 0;
+                mem_write = 0;
+                if (`lag(mem_read_valid)) begin
                     state = FETCH;
-                    {opcode, operand} = mem_read_data_;
+                    {opcode, operand} = `lag(mem_read_data);
                     sign_extended_operand = {{(DATA_BITS-8){operand[7]}}, operand};
                     case (opcode)
                         'h0: begin
@@ -150,7 +135,7 @@ always_ff @(posedge clk) begin
                             end
                         end
                         'h6: begin
-                            mem_write_data_ = acc % 10 + 'h30;
+                            mem_write_data = acc % 10 + 'h30;
                             acc = acc / 10;
                             address = {7'b0, operand[6:0]};
                             state = operand[7] ? INDIRECT : AGEN;
@@ -160,70 +145,70 @@ always_ff @(posedge clk) begin
             end
 
             INDIRECT: begin
-                mem_valid_ = 1;
-                mem_write_ = 0;
-                mem_address_ = address;
-                state = mem_ready_ ? INDIRECTED : INDIRECT;
+                mem_valid = 1;
+                mem_write = 0;
+                mem_address = address;
+                state = `lag(mem_ready) ? INDIRECTED : INDIRECT;
             end
 
             INDIRECTED: begin
-                if (mem_ready_) begin
-                    mem_valid_ = 0;
-                    mem_write_ = 0;
+                if (`lag(mem_ready)) begin
+                    mem_valid = 0;
+                    mem_write = 0;
                 end
-                if (mem_read_valid_) begin
-                    address = {{(ADDR_BITS - DATA_BITS){1'b0}}, mem_read_data_};
+                if (`lag(mem_read_valid)) begin
+                    address = {{(ADDR_BITS - DATA_BITS){1'b0}}, `lag(mem_read_data)};
                     state = AGEN;
                 end
             end
 
             AGEN: begin
-                mem_valid_ = 0;
-                mem_write_ = 0;
+                mem_valid = 0;
+                mem_write = 0;
                 state = FETCH;
                 case (opcode)
                     'h2: begin
-                        mem_valid_ = 1;
-                        mem_address_ = address;
-                        state = mem_ready_ ? MEMORY : AGEN;
+                        mem_valid = 1;
+                        mem_address = address;
+                        state = `lag(mem_ready) ? MEMORY : AGEN;
                     end
                     'h3: begin
-                        mem_valid_ = 1;
-                        mem_address_ = address;
-                        mem_write_ = 1;
-                        mem_write_data_ = acc;
-                        state = mem_ready_ ? FETCH : AGEN;
+                        mem_valid = 1;
+                        mem_address = address;
+                        mem_write = 1;
+                        mem_write_data = acc;
+                        state = `lag(mem_ready) ? FETCH : AGEN;
                     end
                     'h5: pc = address;
                     'h6: begin
-                        mem_valid_ = 1;
-                        mem_address_ = address;
-                        mem_write_ = 1;
-                        state = mem_ready_ ? FETCH : AGEN;
+                        mem_valid = 1;
+                        mem_address = address;
+                        mem_write = 1;
+                        state = `lag(mem_ready) ? FETCH : AGEN;
                     end
                 endcase
             end
 
             MEMORY: begin
-                if (mem_ready_) begin
-                    mem_valid_ = 0;
-                    mem_write_ = 0;
+                if (`lag(mem_ready)) begin
+                    mem_valid = 0;
+                    mem_write = 0;
                 end
                 state = FETCH;
                 case (opcode)
                     'h0: begin
                         if (operand[6]) begin
-                            if (tx_valid_) begin
+                            if (tx_valid) begin
                                 state = MEMORY;
                             end else begin
-                                tx_valid_ = 1;
-                                tx_data_ = acc[7:0];
+                                tx_valid = 1;
+                                tx_data = acc[7:0];
                             end
                         end
                     end
                     'h2: begin
-                        if (mem_read_valid_) begin
-                            acc = acc + mem_read_data_;
+                        if (`lag(mem_read_valid)) begin
+                            acc = acc + `lag(mem_read_data);
                         end else begin
                             state = MEMORY;
                         end
diff --git a/hdl/util.svh b/hdl/util.svh
index fa6ddc5..012e2ed 100644
--- a/hdl/util.svh
+++ b/hdl/util.svh
@@ -1,2 +1,5 @@
-`define input(x) type(x) x``_; assign x``_ = x;
-`define output(x) type(x) x``_; assign x = x``_;
+`ifdef SYNTHESIS
+`define lag(x) x
+`else
+`define lag(x) $past(x)
+`endif
-- 
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