From 7a1311c16c36b18a66a5ee43511fb9ad5093ec3a Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Sun, 28 Mar 2021 14:48:30 -0700 Subject: Initial commit. --- .gitignore | 1 + Makefile | 16 ++++++++++ altera/clocks.sdc | 3 ++ altera/jtag.cdf | 12 ++++++++ build.bat | 7 +++++ clean.bat | 1 + hdl/jtag_uart.sv | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++ hdl/top.sv | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ hdl/util.svh | 5 ++++ init.bat | 5 ++++ mem/jtag_uart.hex | 3 ++ mem/mem.hex | 18 +++++++++++ olamic-run | 12 ++++++++ sim/main.cpp | 56 ++++++++++++++++++++++++++++++++++ tcl/clean.tcl | 3 ++ tcl/init.tcl | 41 +++++++++++++++++++++++++ 16 files changed, 356 insertions(+) create mode 100644 .gitignore create mode 100644 Makefile create mode 100644 altera/clocks.sdc create mode 100644 altera/jtag.cdf create mode 100644 build.bat create mode 100644 clean.bat create mode 100644 hdl/jtag_uart.sv create mode 100644 hdl/top.sv create mode 100644 hdl/util.svh create mode 100644 init.bat create mode 100644 mem/jtag_uart.hex create mode 100644 mem/mem.hex create mode 100644 olamic-run create mode 100644 sim/main.cpp create mode 100644 tcl/clean.tcl create mode 100644 tcl/init.tcl diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..796b96d --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +/build diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..f4a0da8 --- /dev/null +++ b/Makefile @@ -0,0 +1,16 @@ +SOURCES := $(shell find -name \*.sv -o -name \*.cpp) +COLLATERAL := $(shell find -name \*.hex -o -name \*.svh) + +OPTS ?= + +sim: build/Vtop + $< +.PHONY: sim + +build/Vtop: $(SOURCES) $(COLLATERAL) + @mkdir -p build + verilator +1800-2017ext+sv -Wall -Wno-BLKSEQ -Wno-UNUSED -O3 -Ihdl $(OPTS) --Mdir build --trace --cc --build -j --exe --top-module top $(SOURCES) + +clean: + rm -rf build +.PHONY: clean diff --git a/altera/clocks.sdc b/altera/clocks.sdc new file mode 100644 index 0000000..239c91a --- /dev/null +++ b/altera/clocks.sdc @@ -0,0 +1,3 @@ +# This is the clock for timing analysis, not timing-driven synthesis. +# See init.tcl for the other clock. +create_clock -period "50 MHz" clk diff --git a/altera/jtag.cdf b/altera/jtag.cdf new file mode 100644 index 0000000..ac80090 --- /dev/null +++ b/altera/jtag.cdf @@ -0,0 +1,12 @@ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Ign) + Device PartName(10CL025Y) MfrSpec(OpMask(0)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/build.bat b/build.bat new file mode 100644 index 0000000..76cb8ff --- /dev/null +++ b/build.bat @@ -0,0 +1,7 @@ +if not exist noncpu.qpf ( + call init.bat +) else ( + call clean.bat +) + +quartus_sh.exe --flow compile noncpu diff --git a/clean.bat b/clean.bat new file mode 100644 index 0000000..6b31ea1 --- /dev/null +++ b/clean.bat @@ -0,0 +1 @@ +quartus_sh -t tcl/clean.tcl diff --git a/hdl/jtag_uart.sv b/hdl/jtag_uart.sv new file mode 100644 index 0000000..ad4665e --- /dev/null +++ b/hdl/jtag_uart.sv @@ -0,0 +1,84 @@ +`include "util.svh" + +module jtag_uart + #( INSTANCE = 0 + + , RX_FIFO_BITS = 6 + , TX_FIFO_BITS = 6 + ) + ( input bit clk + , input bit reset + + , input bit rx_ready `define rx_ready `past(rx_ready) + , output bit rx_valid + , output bit [7:0] rx_data + + , output bit tx_ready + , input bit tx_valid `define tx_valid `past(tx_valid) + , input bit [7:0] tx_data `define tx_data `past(tx_data) + ); + +`ifdef SYNTHESIS + +alt_jtag_atlantic + #( .INSTANCE_ID(INSTANCE) + , .LOG2_RXFIFO_DEPTH(RX_FIFO_BITS) + , .LOG2_TXFIFO_DEPTH(TX_FIFO_BITS) + , .SLD_AUTO_INSTANCE_INDEX("NO") + ) real_jtag + ( .clk(clk) + , .rst_n(!reset) + , .r_dat(tx_data) + , .r_val(tx_valid) + , .r_ena(tx_ready) + , .t_dat(rx_data) + , .t_dav(rx_ready) + , .t_ena(rx_valid) + ); + +`else + +bit [7:0] sim_rx_rom [0:(1<<16)-1]; +initial $readmemh("mem/jtag_uart.hex", sim_rx_rom); + +bit [15:0] sim_rx_addr; + +bit tx_b_valid; +bit [7:0] tx_b_data; + +always_ff @(posedge clk) begin + if (reset) begin + rx_valid = 0; + tx_ready = 0; + sim_rx_addr = 0; + tx_b_valid = 0; + end else begin + automatic bit [7:0] sim_rx_data = sim_rx_rom[sim_rx_addr]; + + // RX logic + if (`rx_ready) rx_valid = 0; + if (!rx_valid && (sim_rx_data != 0)) begin +`ifdef JTAG_UART_LOCAL_ECHO + $write("%s", sim_rx_data); +`endif + rx_valid = 1; + rx_data = sim_rx_data; + ++sim_rx_addr; + end + + // TX logic + if (tx_ready && `tx_valid) begin + tx_b_valid = 1; + tx_b_data = `tx_data; + end + if (tx_b_valid) begin + $write("%s", tx_b_data); + tx_b_valid = 0; + end + tx_ready = !tx_b_valid; + end +end + +`endif + +endmodule diff --git a/hdl/top.sv b/hdl/top.sv new file mode 100644 index 0000000..8524b63 --- /dev/null +++ b/hdl/top.sv @@ -0,0 +1,89 @@ +`include "util.svh" + +module top + #( ADDR_BITS = 14 + , DATA_BITS = 12 + ) + ( input bit clk // verilator public + , input bit reset_n // verilator public + ); + +bit reset = 0; +bit have_reset = 0; +always_ff @(posedge clk) if (reset) have_reset <= 1; +assign reset = !reset_n || !have_reset; + +bit [DATA_BITS-1:0] mem [0:(1< +#include +#include +#include + +#include "Vtop.h" + +int main(int argc, const char *argv[]) +{ + Verilated::commandArgs(argc, argv); + + Verilated::traceEverOn(true); + VerilatedVcdC vcd; + + Vtop top; + top.trace(&vcd, 100 /* levels of hierarchy */); + + vcd.set_time_unit("ns"); + vcd.set_time_resolution("ns"); + vcd.open("build/out.vcd"); + + std::cout << "*** RESET SEQUENCE ***\n"; + + std::uint64_t time = 0; + + top.clk = 0; + top.reset_n = 0; + top.eval(); + vcd.dump(++time); + + top.clk = 1; + top.eval(); + vcd.dump(++time); + + top.clk = 0; + top.reset_n = 1; + top.eval(); + vcd.dump(++time); + + std::cout << "*** MAIN LOOP ***\n"; + + for (unsigned int i = 0; i < 500 && !Verilated::gotFinish(); ++i) { + top.clk = 1; + top.eval(); + vcd.dump(++time); + top.clk = 0; + top.eval(); + vcd.dump(++time); + } + + std::cout << "\n"; + + vcd.close(); + + return 0; +} diff --git a/tcl/clean.tcl b/tcl/clean.tcl new file mode 100644 index 0000000..49c9f65 --- /dev/null +++ b/tcl/clean.tcl @@ -0,0 +1,3 @@ +project_open noncpu -revision noncpu + +project_clean -revision noncpu diff --git a/tcl/init.tcl b/tcl/init.tcl new file mode 100644 index 0000000..039af91 --- /dev/null +++ b/tcl/init.tcl @@ -0,0 +1,41 @@ +project_new noncpu -revision noncpu -overwrite + +set_global_assignment -name DEVICE 10CL025YU256I7G + +set_global_assignment -name TOP_LEVEL_ENTITY top +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1" + +proc pin {loc net} { + set_location_assignment -to $net "PIN_$loc" + set_instance_assignment -name IO_STANDARD "3.3V LVTTL" -to $net +} + +pin E1 clk +pin J15 reset_n + +# This is the clock for timing-driven synthesis, not timing analysis. +# See clocks.sdf for the other clock. +create_base_clock -fmax "50 MHz" clk + +proc add_files {typ ext dir} { + foreach name [glob -nocomplain -directory $dir -type f "*.$ext"] { + set_global_assignment -name "${typ}_FILE" $name + } +} + +proc add_dir {dir} { + add_files CDF cdf $dir + add_files HEX hex $dir + add_files SDC sdc $dir + add_files VERILOG sv $dir + add_files VERILOG svh $dir + + foreach subdir [glob -nocomplain -directory $dir -type d *] { + add_dir $subdir + } +} + +add_dir . + +project_close -- cgit v1.2.3