From eb383e57277f7628c6ecca629637bb6ddfbe5b38 Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Sun, 24 Oct 2021 12:31:54 -0700 Subject: Blinkenlights. --- hdl/panel.sv | 184 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ hdl/top.sv | 56 ++++++++++++++++++ tcl/init.tcl | 49 +++++++++++++++- 3 files changed, 286 insertions(+), 3 deletions(-) create mode 100644 hdl/panel.sv diff --git a/hdl/panel.sv b/hdl/panel.sv new file mode 100644 index 0000000..fc1f718 --- /dev/null +++ b/hdl/panel.sv @@ -0,0 +1,184 @@ +`include "util.svh" + +module panel + ( input bit clk + , input bit reset + + , input bit [8:1][12:1] led + , output bit [3:1][12:1] switch + + , inout wire [10:1] gpioa + , inout wire [28:13] gpiob + , inout wire [40:31] gpioc + ); + +enum + { LED_ROW1 + , LED_ROW2 + , LED_ROW3 + , LED_ROW4 + , LED_ROW5 + , LED_ROW6 + , LED_ROW7 + , LED_ROW8 + , SWITCH_PREP + , SWITCH_ROW1 + , SWITCH_ROW2 + , SWITCH_ROW3 + } state; + +`define LEDROW1 gpioc[38] +`define LEDROW2 gpioc[40] +`define LEDROW3 gpiob[15] +`define LEDROW4 gpiob[16] +`define LEDROW5 gpiob[18] +`define LEDROW6 gpiob[22] +`define LEDROW7 gpioc[37] +`define LEDROW8 gpiob[13] + +`define SWROW1 gpioc[36] +`define SWROW2 gpioa[1] +`define SWROW3 gpioa[2] + +`define COL1 gpioa[8] +`define COL2 gpioa[10] +`define COL3 gpioa[7] +`define COL4 gpiob[27] +`define COL5 gpioc[31] +`define COL6 gpiob[26] +`define COL7 gpiob[24] +`define COL8 gpiob[21] +`define COL9 gpiob[19] +`define COL10 gpiob[23] +`define COL11 gpioc[32] +`define COL12 gpioc[33] + +`define DO_LEDS +`define DO_SWITCHES + +always_ff @(posedge clk) begin + // LED rows (active high) + `LEDROW1 = 1'b0; + `LEDROW2 = 1'b0; + `LEDROW3 = 1'b0; + `LEDROW4 = 1'b0; + `LEDROW5 = 1'b0; + `LEDROW6 = 1'b0; + `LEDROW7 = 1'b0; + `LEDROW8 = 1'b0; + + // Switch rows (active low) + `SWROW1 = 1'b1; + `SWROW2 = 1'b1; + `SWROW3 = 1'b1; + + if (reset) begin + switch = 0; + state = state.first; + end else begin + case (state) +`ifdef DO_LEDS +`define LED_ROW(n) \ + LED_ROW``n: begin \ + `LEDROW``n = 1'b1; \ + `COL1 = ~led[n][1]; \ + `COL2 = ~led[n][2]; \ + `COL3 = ~led[n][3]; \ + `COL4 = ~led[n][4]; \ + `COL5 = ~led[n][5]; \ + `COL6 = ~led[n][6]; \ + `COL7 = ~led[n][7]; \ + `COL8 = ~led[n][8]; \ + `COL9 = ~led[n][9]; \ + `COL10 = ~led[n][10]; \ + `COL11 = ~led[n][11]; \ + `COL12 = ~led[n][12]; \ + end + + `LED_ROW(1) + `LED_ROW(2) + `LED_ROW(3) + `LED_ROW(4) + `LED_ROW(5) + `LED_ROW(6) + `LED_ROW(7) + `LED_ROW(8) +`endif + +`ifdef DO_SWITCHES + SWITCH_PREP: begin + `SWROW1 = 1'b0; + + `COL1 = 1'bZ; + `COL2 = 1'bZ; + `COL3 = 1'bZ; + `COL4 = 1'bZ; + `COL5 = 1'bZ; + `COL6 = 1'bZ; + `COL7 = 1'bZ; + `COL8 = 1'bZ; + `COL9 = 1'bZ; + `COL10 = 1'bZ; + `COL11 = 1'bZ; + `COL12 = 1'bZ; + end + + SWITCH_ROW1: begin + `SWROW2 = 1'b0; + + switch[1][1] = ~`COL1; + switch[1][2] = ~`COL2; + switch[1][3] = ~`COL3; + switch[1][4] = ~`COL4; + switch[1][5] = ~`COL5; + switch[1][6] = ~`COL6; + switch[1][7] = ~`COL7; + switch[1][8] = ~`COL8; + switch[1][9] = ~`COL9; + switch[1][10] = ~`COL10; + switch[1][11] = ~`COL11; + switch[1][12] = ~`COL12; + end + + SWITCH_ROW2: begin + `SWROW3 = 1'b0; + + switch[2][1] = ~`COL1; + switch[2][2] = ~`COL2; + switch[2][3] = ~`COL3; + switch[2][4] = ~`COL4; + switch[2][5] = ~`COL5; + switch[2][6] = ~`COL6; + switch[2][7] = ~`COL7; + switch[2][8] = ~`COL8; + switch[2][9] = ~`COL9; + switch[2][10] = ~`COL10; + switch[2][11] = ~`COL11; + switch[2][12] = ~`COL12; + end + + SWITCH_ROW3: begin + switch[3][1] = ~`COL1; + switch[3][2] = ~`COL2; + switch[3][3] = ~`COL3; + switch[3][4] = ~`COL4; + switch[3][5] = ~`COL5; + switch[3][6] = ~`COL6; + switch[3][7] = ~`COL7; + switch[3][8] = ~`COL8; + switch[3][9] = ~`COL9; + switch[3][10] = ~`COL10; + switch[3][11] = ~`COL11; + switch[3][12] = ~`COL12; + end +`endif + endcase + + if (state == state.last) + state = state.first; + else + state = state.next; + end +end + +endmodule diff --git a/hdl/top.sv b/hdl/top.sv index 1d77216..abd6f30 100644 --- a/hdl/top.sv +++ b/hdl/top.sv @@ -3,6 +3,10 @@ module top ( input bit native_clk // verilator public , input bit reset_n // verilator public + + , inout wire [10:1] gpioa + , inout wire [28:13] gpiob + , inout wire [40:31] gpioc ); bit clk; @@ -18,9 +22,61 @@ clock , .reset(reset) ); +bit slowclk; +bit slowreset; +clock + #( .MULTIPLY_BY(1) + , .DIVIDE_BY(5000) + ) slowpll + ( .native_clk(native_clk) + , .reset_n(reset_n) + , .target_clk(slowclk) + , .reset(slowreset) + ); + +bit [8:1][12:1] led; +bit [3:1][12:1] switch; + +panel fp + ( .clk(slowclk) + , .reset(slowreset) + + , .led(led) + , .switch(switch) + + , .gpioa(gpioa) + , .gpiob(gpiob) + , .gpioc(gpioc) + ); + +assign led[1] = switch[1]; +assign led[2] = switch[2]; +assign led[3] = switch[3]; +assign led[4] = 0; +assign led[5] = 0; +assign led[6] = 0; +assign led[7] = 0; +assign led[8] = 0; + +/* +wire [7:0] debugchar; +assign debugchar = "0" + {switch[1][1], switch[1][2], switch[3][1]}; + +jtag_uart debug + ( .clk(slowclk) + , .reset(slowreset) + + , .rx_ready(0) + , .tx_valid(1) + , .tx_data(debugchar) + ); +*/ + +/* core cpu ( .clk(clk) , .reset(reset) ); +*/ endmodule diff --git a/tcl/init.tcl b/tcl/init.tcl index 3466f17..9f296f3 100644 --- a/tcl/init.tcl +++ b/tcl/init.tcl @@ -6,13 +6,56 @@ set_global_assignment -name TOP_LEVEL_ENTITY top set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1" -proc pin {loc net} { +proc pin {net loc} { set_location_assignment -to $net "PIN_$loc" set_instance_assignment -name IO_STANDARD "3.3V LVTTL" -to $net } -pin E1 native_clk -pin J15 reset_n +proc iopin {net loc} { + pin $net $loc + set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to $net +} + +pin native_clk E1 + +iopin reset_n J15 + +iopin gpioa[1] L13 +iopin gpioa[2] L16 +iopin gpioa[3] L15 +iopin gpioa[4] K16 +iopin gpioa[5] P16 +iopin gpioa[6] R16 +iopin gpioa[7] N16 +iopin gpioa[8] N15 +iopin gpioa[9] N14 +iopin gpioa[10] P15 +iopin gpiob[13] N8 +iopin gpiob[14] P8 +iopin gpiob[15] M8 +iopin gpiob[16] L8 +iopin gpiob[17] R7 +iopin gpiob[18] T7 +iopin gpiob[19] L7 +iopin gpiob[20] M7 +iopin gpiob[21] R6 +iopin gpiob[22] T6 +iopin gpiob[23] T2 +iopin gpiob[24] M6 +iopin gpiob[25] R5 +iopin gpiob[26] T5 +iopin gpiob[27] N5 +iopin gpiob[28] N6 +iopin gpioc[31] R4 +iopin gpioc[32] T4 +iopin gpioc[33] N3 +iopin gpioc[34] P3 +iopin gpioc[35] R3 +iopin gpioc[36] T3 +iopin gpioc[37] P6 +iopin gpioc[38] P2 +iopin gpioc[39] P1 +iopin gpioc[40] R1 # This is the clock for timing-driven synthesis, not timing analysis. # See clocks.sdf for the other clock. -- cgit v1.2.3