From 4203007c5ac99c6f46b2aea378d043511b2d798d Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Thu, 15 Apr 2021 16:39:30 -0700
Subject: Fix timing declarations for PLL in Quartus assignments.

---
 altera/clocks.sdc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'altera/clocks.sdc')

diff --git a/altera/clocks.sdc b/altera/clocks.sdc
index 15d4482..1febf5c 100644
--- a/altera/clocks.sdc
+++ b/altera/clocks.sdc
@@ -1,3 +1,4 @@
 # This is the clock for timing analysis, not timing-driven synthesis.
 # See init.tcl for the other clock.
+create_clock -period "50 MHz" native_clk
 create_clock -period "45 MHz" clk
-- 
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