From 15daf2fe9fd13e18609b2141c3346fec6389bda9 Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Sun, 24 Oct 2021 15:02:31 -0700 Subject: More blinkenlights work. --- hdl/core.sv | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 69 insertions(+), 4 deletions(-) (limited to 'hdl/core.sv') diff --git a/hdl/core.sv b/hdl/core.sv index 1b61944..c0e1a63 100644 --- a/hdl/core.sv +++ b/hdl/core.sv @@ -6,21 +6,58 @@ module core ) ( input bit clk , input bit reset + + , input bit switch_cont + + , output bit [0:ADDR_BITS-1] led_pc + , output bit [0:ADDR_BITS-1] led_memaddr + , output bit [0:DATA_BITS-1] led_memdata + , output bit [0:DATA_BITS-1] led_acc + , output bit [0:DATA_BITS-1] led_mq + , output bit led_and + , output bit led_tad + , output bit led_isz + , output bit led_dca + , output bit led_jms + , output bit led_jmp + , output bit led_iot + , output bit led_opr + , output bit led_fetch + , output bit led_execute + , output bit led_defer + , output bit led_word_count + , output bit led_current_address + , output bit led_break + , output bit led_ion + , output bit led_pause + , output bit led_run + , output bit [0:4] led_step_counter + , output bit [0:2] led_df + , output bit [0:2] led_if + , output bit led_link ); +bit run; +assign led_run = run; + bit mem_ready; bit mem_valid; bit mem_write; bit [ADDR_BITS-1:0] mem_address; bit [DATA_BITS-1:0] mem_write_data; +assign led_df = 0; +assign led_if = 0; +assign led_memaddr = mem_address; + bit mem_read_valid; bit [DATA_BITS-1:0] mem_read_data; mem #( .ADDR_BITS(ADDR_BITS) , .DATA_BITS(DATA_BITS) - , .INIT_FILE("mem/focal69.loaded.hex") +// , .INIT_FILE("mem/focal69.loaded.hex") + , .INIT_FILE("build/mem/hello.hex") ) memory ( .clk(clk) @@ -67,6 +104,19 @@ bit [8:0] operand; bit [DATA_BITS-1:0] acc; bit link; +assign led_pc = pc; +assign led_acc = acc; +assign led_link = link; + +assign led_and = opcode == 0; +assign led_tad = opcode == 1; +assign led_isz = opcode == 2; +assign led_dca = opcode == 3; +assign led_jms = opcode == 4; +assign led_jmp = opcode == 5; +assign led_iot = opcode == 6; +assign led_opr = opcode == 7; + bit kbd_valid; bit [DATA_BITS-1:0] kbd_data; @@ -87,8 +137,14 @@ enum , HALT } state; +assign led_fetch = state == FETCH || state == DECODE; +assign led_execute = state == AGEN || state == EXEC; +assign led_defer = state == INDIRECT || state == INDIRECTED || state == PREINC; +assign led_pause = state == MEMWAIT || state == HALT; + always_ff @(posedge clk) begin if (reset) begin + run = 0; mem_valid = 0; rx_ready = 0; tx_valid = 0; @@ -98,7 +154,9 @@ always_ff @(posedge clk) begin link = 1; kbd_valid = 0; state = state.first; - end else begin + end else if (run || switch_cont) begin + run = 1; + if (`lag(tx_ready)) tx_valid = 0; if (rx_ready && `lag(rx_valid)) begin kbd_valid = 1; @@ -122,6 +180,7 @@ always_ff @(posedge clk) begin mem_write = 0; if (`lag(mem_read_valid)) begin state = FETCH; + led_memdata = `lag(mem_read_data); {opcode, operand} = `lag(mem_read_data); // $display("%o: decode %o %o", pc-1, opcode, operand); // verilator lint_off WIDTH @@ -261,10 +320,12 @@ always_ff @(posedge clk) begin end if (`lag(mem_read_valid)) begin if (address[7:3] == 5'b00001) begin + led_memdata = `lag(mem_read_data); address = {{(ADDR_BITS - DATA_BITS){1'b0}}, `lag(mem_read_data)}; address += 1; state = PREINC; end else begin + led_memdata = `lag(mem_read_data); address = {{(ADDR_BITS - DATA_BITS){1'b0}}, `lag(mem_read_data)}; case (opcode) 'o0, 'o1, 'o2: state = AGEN; @@ -282,6 +343,7 @@ always_ff @(posedge clk) begin mem_valid = 1; mem_write = 1; mem_write_data = address[DATA_BITS-1:0]; + led_memdata = mem_write_data; case (opcode) 'o0, 'o1, 'o2: state = `lag(mem_ready) ? AGEN : PREINC; 'o3, 'o4, 'o5: state = `lag(mem_ready) ? EXEC : PREINC; @@ -311,13 +373,14 @@ always_ff @(posedge clk) begin if (! stall) begin state = FETCH; case (opcode) - 'o0: acc &= `lag(mem_read_data); - 'o1: {link, acc} += {1'b0, `lag(mem_read_data)}; + 'o0: begin led_memdata = `lag(mem_read_data); acc &= `lag(mem_read_data); end + 'o1: begin led_memdata = `lag(mem_read_data); {link, acc} += {1'b0, `lag(mem_read_data)}; end 'o2: begin mem_valid = 1; mem_address = address; mem_write = 1; mem_write_data = `lag(mem_read_data) + 1; + led_memdata = mem_write_data; if (mem_write_data == 0) ++pc; state = MEMWAIT; end @@ -326,6 +389,7 @@ always_ff @(posedge clk) begin mem_address = address; mem_write = 1; mem_write_data = acc; + led_memdata = mem_write_data; acc = 0; state = MEMWAIT; end @@ -334,6 +398,7 @@ always_ff @(posedge clk) begin mem_address = address; mem_write = 1; mem_write_data = pc[DATA_BITS-1:0]; + led_memdata = mem_write_data; pc = address + 1; state = MEMWAIT; end -- cgit v1.2.3