From 56eb00d755a3ff2647d635ea9d9ea2e1dd9e15c8 Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Sun, 16 May 2021 13:40:27 -0700 Subject: Work in progress from May 9 --- hdl/core.sv | 80 +++++++++++++++++++++++++++++++++---------------------------- 1 file changed, 44 insertions(+), 36 deletions(-) (limited to 'hdl/core.sv') diff --git a/hdl/core.sv b/hdl/core.sv index 7edf523..12b5459 100644 --- a/hdl/core.sv +++ b/hdl/core.sv @@ -20,7 +20,7 @@ bit [DATA_BITS-1:0] mem_read_data; mem #( .ADDR_BITS(ADDR_BITS) , .DATA_BITS(DATA_BITS) - , .INIT_FILE("build/mem/hello.hex") + , .INIT_FILE("mem/focal69.loaded.hex") ) memory ( .clk(clk) @@ -95,7 +95,7 @@ always_ff @(posedge clk) begin tx_data = 0; pc = 'o200; acc = 0; - link = 0; + link = 1; kbd_valid = 0; state = state.first; end else begin @@ -123,23 +123,26 @@ always_ff @(posedge clk) begin if (`lag(mem_read_valid)) begin state = FETCH; {opcode, operand} = `lag(mem_read_data); - //$display("%d decode %x: %b %b", $time, pc-1, opcode, operand); +// $display("%o: decode %o %o", pc-1, opcode, operand); +// // verilator lint_off WIDTH +// $display("%o %b %o 0000", 14'(pc-1), link, acc); +// // verilator lint_on WIDTH {i, z, wip} = operand; if (z) address = {page, wip}; else address = {5'b0, wip}; case (opcode) - 'b000, 'b001, 'b010: state = i ? INDIRECT : AGEN; - 'b011, 'b100: state = i ? INDIRECT : EXEC; - 'b101: begin + 'o0, 'o1, 'o2: state = i ? INDIRECT : AGEN; + 'o3, 'o4: state = i ? INDIRECT : EXEC; + 'o5: begin if (i) begin state = INDIRECT; end else begin pc = address; end end - 'b111: begin + 'o7: begin casez (operand) 'b0????????: begin automatic bit cla, cll, cma, cml, rar, ral, bsw, iac; @@ -170,7 +173,7 @@ always_ff @(posedge clk) begin if (skip) pc++; if (cla) acc = 0; if (osr) begin - $display("unsupported front panel switch test"); + $display("%o: unsupported front panel switch test", pc); $finish; end if (hlt) state = HALT; @@ -186,53 +189,58 @@ always_ff @(posedge clk) begin if (skip && (spa || sna || szl)) pc++; if (cla) acc = 0; if (osr) begin - $display("unsupported front panel switch test"); + $display("%o: unsupported front panel switch test", pc); $finish; end if (hlt) state = HALT; end default: begin - $display("%d decoded unknown opcode %x: %b %b", $time, pc-1, opcode, operand); + $display("%o: decoded unknown opcode %o %o", pc-1, opcode, operand); $finish; end endcase end - 'b110: begin + 'o6: begin case (operand[8:3]) - 'b000011: begin + 'o00: begin case (operand[2:0]) - 'b001: if (kbd_valid) pc++; - 'b110: begin + 'o0, 'o1: ; + default: $display("%o: unsupported 600%o op", pc-1, operand[2:0]); + endcase + end + 'o03: begin + case (operand[2:0]) + 'o1: if (kbd_valid) pc++; + 'o6: begin acc = kbd_data; kbd_valid = 0; end default: begin - $display("unsupported keyboard op %b", operand[2:0]); + $display("%o: unsupported keyboard op %o", pc-1, operand[2:0]); $finish; end endcase end - 'b000100: begin + 'o04: begin case (operand[2:0]) - 'b001: if (!tx_valid) pc++; - 'b110: begin + 'o1: if (!tx_valid) pc++; + 'o6: begin tx_valid = 1; tx_data = {1'b0, acc[6:0]}; end default: begin - $display("unsupported tty op %b", operand[2:0]); + $display("%o: unsupported tty op %o", pc-1, operand[2:0]); $finish; end endcase end default: begin - $display("unsupported device %b", operand[8:3]); - $finish; + $display("%o: unsupported device %o (operation %o)", pc-1, operand[8:3], operand[2:0]); end endcase end default: begin - $display("%d decoded unknown opcode %x: %b %b", $time, pc-1, opcode, operand); + $display("%o: decoded unknown opcode %o %o", pc-1, opcode, operand); $finish; end endcase @@ -259,9 +267,9 @@ always_ff @(posedge clk) begin end else begin address = {{(ADDR_BITS - DATA_BITS){1'b0}}, `lag(mem_read_data)}; case (opcode) - 'b000, 'b001, 'b010: state = AGEN; - 'b011, 'b100: state = EXEC; - 'b101: begin + 'o0, 'o1, 'o2: state = AGEN; + 'o3, 'o4: state = EXEC; + 'o5: begin pc = address; state = FETCH; end @@ -275,15 +283,15 @@ always_ff @(posedge clk) begin mem_write = 1; mem_write_data = address[DATA_BITS-1:0]; case (opcode) - 'b000, 'b001, 'b010: state = `lag(mem_ready) ? AGEN : PREINC; - 'b011, 'b100, 'b101: state = `lag(mem_ready) ? EXEC : PREINC; + 'o0, 'o1, 'o2: state = `lag(mem_ready) ? AGEN : PREINC; + 'o3, 'o4, 'o5: state = `lag(mem_ready) ? EXEC : PREINC; endcase end AGEN: begin mem_valid = 1; case (opcode) - 'b000, 'b001, 'b010: mem_write = 0; + 'o0, 'o1, 'o2: mem_write = 0; endcase mem_address = address; state = `lag(mem_ready) ? EXEC : AGEN; @@ -298,14 +306,14 @@ always_ff @(posedge clk) begin stall = 1; end case (opcode) - 'b000, 'b001, 'b010: if (! `lag(mem_read_valid)) stall = 1; + 'o0, 'o1, 'o2: if (! `lag(mem_read_valid)) stall = 1; endcase if (! stall) begin state = FETCH; case (opcode) - 'b000: acc &= `lag(mem_read_data); - 'b001: {link, acc} += {1'b0, `lag(mem_read_data)}; - 'b010: begin + 'o0: acc &= `lag(mem_read_data); + 'o1: {link, acc} += {1'b0, `lag(mem_read_data)}; + 'o2: begin mem_valid = 1; mem_address = address; mem_write = 1; @@ -313,7 +321,7 @@ always_ff @(posedge clk) begin if (mem_write_data == 0) ++pc; state = MEMWAIT; end - 'b011: begin + 'o3: begin mem_valid = 1; mem_address = address; mem_write = 1; @@ -321,7 +329,7 @@ always_ff @(posedge clk) begin acc = 0; state = MEMWAIT; end - 'b100: begin + 'o4: begin mem_valid = 1; mem_address = address; mem_write = 1; @@ -329,7 +337,7 @@ always_ff @(posedge clk) begin pc = address + 1; state = MEMWAIT; end - 'b101: pc = address; + 'o5: pc = address; endcase end end @@ -337,7 +345,7 @@ always_ff @(posedge clk) begin MEMWAIT: state = `lag(mem_ready) ? FETCH : MEMWAIT; HALT: begin - $display("%d halt state reached", $time); + $display("\nhalt state reached"); $finish; end endcase -- cgit v1.2.3