From a9a3b8f7ab7f2067843a9a642447a9b7270440ce Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 21 Nov 2021 13:28:55 -0800
Subject: Implement switches Start and LoadAdd.

---
 hdl/core.sv | 56 +++++++++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 53 insertions(+), 3 deletions(-)

(limited to 'hdl/core.sv')

diff --git a/hdl/core.sv b/hdl/core.sv
index 43a4a1a..14660f5 100644
--- a/hdl/core.sv
+++ b/hdl/core.sv
@@ -7,6 +7,13 @@ module core
     (   input   bit clk
     ,   input   bit reset
 
+    ,   input   bit [2:0] switch_df
+    ,   input   bit [2:0] switch_if
+    ,   input   bit [ADDR_BITS-1:0] switch_sr
+    ,   input   bit switch_start
+    ,   input   bit switch_load_add
+    ,   input   bit switch_dep
+    ,   input   bit switch_exam
     ,   input   bit switch_cont
     ,   input   bit switch_stop
     ,   input   bit switch_sing_step
@@ -43,6 +50,10 @@ module core
     );
 
 bit run;
+bit switch_start_observed;
+bit switch_load_add_observed;
+bit switch_dep_observed;
+bit switch_exam_observed;
 bit switch_cont_observed;
 assign led_run = run;
 
@@ -53,8 +64,8 @@ bit [ADDR_BITS-1:0] mem_address;
 bit [DATA_BITS-1:0] mem_write_data;
 assign led_current_address = mem_valid;
 
-assign led_df = 0;
-assign led_if = 0;
+assign led_df = switch_df; // FIXME actually implement DF and IF
+assign led_if = switch_if;
 assign led_memaddr = mem_address;
 
 bit mem_read_valid;
@@ -151,6 +162,10 @@ assign led_pause = state == MEMWAIT || state == HALT;
 always_ff @(posedge clk) begin
     if (reset) begin
         run = 0;
+        switch_start_observed = 0;
+        switch_load_add_observed = 0;
+        switch_dep_observed = 0;
+        switch_exam_observed = 0;
         switch_cont_observed = 0;
         mem_valid = 0;
         rx_ready = 0;
@@ -163,9 +178,44 @@ always_ff @(posedge clk) begin
         kbd_valid = 0;
         state = state.first;
     end else begin
-        if (switch_cont && !switch_cont_observed) begin
+        if (switch_start && !switch_start_observed) begin
+            switch_start_observed = 1;
             run = 1;
+            mem_valid = 0;
+            acc = 0;
+            link = 1;
+            state = state.first;
+        end
+
+        if (!switch_start)
+            switch_start_observed = 0;
+
+        if (switch_load_add && !switch_load_add_observed) begin
+            switch_load_add_observed = 1;
+            pc = switch_sr;
+            led_pc = pc;
+        end
+
+        if (!switch_load_add)
+            switch_load_add_observed = 0;
+
+        if (switch_dep && !switch_dep_observed) begin
+            switch_dep_observed = 1;
+        end
+
+        if (!switch_dep)
+            switch_dep_observed = 0;
+
+        if (switch_exam && !switch_exam_observed) begin
+            switch_exam_observed = 1;
+        end
+
+        if (!switch_exam)
+            switch_exam_observed = 0;
+
+        if (switch_cont && !switch_cont_observed) begin
             switch_cont_observed = 1;
+            run = 1;
         end
 
         if (!switch_cont)
-- 
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