From 0c9e672cffa935f4db57d99e161a0c22b2b25cd9 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 28 Mar 2021 17:19:12 -0700
Subject: Yet another lame attempt.

---
 hdl/mem.sv | 36 ++++++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 12 deletions(-)

(limited to 'hdl/mem.sv')

diff --git a/hdl/mem.sv b/hdl/mem.sv
index 906870d..9be5c4d 100644
--- a/hdl/mem.sv
+++ b/hdl/mem.sv
@@ -1,12 +1,17 @@
+`include "util.svh"
+
 module mem
     (   input   bit clk
+    ,   input   bit reset
 
     ,   output  bit                 ready
-    ,   input   bit                 valid
-    ,   input   bit                 write
-    ,   input   bit [ADDR_BITS-1:0] address
-    ,   input   bit [DATA_BITS-1:0] write_data
-    ,   output  bit [DATA_BITS-1:0] read_data   // Valid exactly the cycle after address is consumed.
+    ,   input   bit                 valid       `define valid `past(valid)
+    ,   input   bit                 write       `define write `past(write)
+    ,   input   bit [ADDR_BITS-1:0] address     `define address `past(address)
+    ,   input   bit [DATA_BITS-1:0] write_data  `define write_data `past(write_data)
+
+    ,   output  bit                 read_valid
+    ,   output  bit [DATA_BITS-1:0] read_data
     );
 
 parameter ADDR_BITS;
@@ -16,14 +21,21 @@ parameter INIT_FILE;
 bit [DATA_BITS-1:0] storage [0:(1<<ADDR_BITS)-1];
 initial $readmemh(INIT_FILE, storage);
 
-assign ready = 1;
-
 always_ff @(posedge clk) begin
-    if (ready && valid) begin
-        if (write)
-            storage[address] <= write_data;
-        else
-            read_data <= storage[address];
+    if (reset) begin
+        ready = 0;
+        read_valid = 0;
+    end else begin
+        read_valid = 0;
+        if (ready && `valid) begin
+            if (`write) begin
+                storage[`address] = `write_data;
+            end else begin
+                read_valid = 1;
+                read_data = storage[`address];
+            end
+        end
+        ready = 1;
     end
 end
 
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