From 6a1c04608090cc8fc88aafac0b4899e4cbb9cae9 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Mon, 5 Apr 2021 10:20:02 -0700
Subject: Change our simulator timing model to use continuous assignment
 guards.

Instead of depending on verilator getting $past right, this (ab-)uses
the SystemVerilog scheduling model which allows us to get a consistent
view of the universe by "isolating" the blocking updates. Easier to code
to and seems to be more reliable in verilator.
---
 hdl/mem.sv | 34 +++++++++++++++++++++-------------
 1 file changed, 21 insertions(+), 13 deletions(-)

(limited to 'hdl/mem.sv')

diff --git a/hdl/mem.sv b/hdl/mem.sv
index 9be5c4d..c362e37 100644
--- a/hdl/mem.sv
+++ b/hdl/mem.sv
@@ -5,10 +5,10 @@ module mem
     ,   input   bit reset
 
     ,   output  bit                 ready
-    ,   input   bit                 valid       `define valid `past(valid)
-    ,   input   bit                 write       `define write `past(write)
-    ,   input   bit [ADDR_BITS-1:0] address     `define address `past(address)
-    ,   input   bit [DATA_BITS-1:0] write_data  `define write_data `past(write_data)
+    ,   input   bit                 valid
+    ,   input   bit                 write
+    ,   input   bit [ADDR_BITS-1:0] address
+    ,   input   bit [DATA_BITS-1:0] write_data
 
     ,   output  bit                 read_valid
     ,   output  bit [DATA_BITS-1:0] read_data
@@ -18,24 +18,32 @@ parameter ADDR_BITS;
 parameter DATA_BITS;
 parameter INIT_FILE;
 
+`output(ready)
+`input(valid)
+`input(write)
+`input(address)
+`input(write_data)
+`output(read_valid)
+`output(read_data)
+
 bit [DATA_BITS-1:0] storage [0:(1<<ADDR_BITS)-1];
 initial $readmemh(INIT_FILE, storage);
 
 always_ff @(posedge clk) begin
     if (reset) begin
-        ready = 0;
-        read_valid = 0;
+        ready_ = 0;
+        read_valid_ = 0;
     end else begin
-        read_valid = 0;
-        if (ready && `valid) begin
-            if (`write) begin
-                storage[`address] = `write_data;
+        read_valid_ = 0;
+        if (ready_ && valid_) begin
+            if (write_) begin
+                storage[address_] = write_data_;
             end else begin
-                read_valid = 1;
-                read_data = storage[`address];
+                read_valid_ = 1;
+                read_data_ = storage[address_];
             end
         end
-        ready = 1;
+        ready_ = 1;
     end
 end
 
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