From 7a1311c16c36b18a66a5ee43511fb9ad5093ec3a Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 28 Mar 2021 14:48:30 -0700
Subject: Initial commit.

---
 hdl/top.sv | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 hdl/top.sv

(limited to 'hdl/top.sv')

diff --git a/hdl/top.sv b/hdl/top.sv
new file mode 100644
index 0000000..8524b63
--- /dev/null
+++ b/hdl/top.sv
@@ -0,0 +1,89 @@
+`include "util.svh"
+
+module top
+    #(  ADDR_BITS   = 14
+    ,   DATA_BITS   = 12
+    )
+    (   input   bit clk     // verilator public
+    ,   input   bit reset_n // verilator public
+    );
+
+bit reset = 0;
+bit have_reset = 0;
+always_ff @(posedge clk) if (reset) have_reset <= 1;
+assign reset = !reset_n || !have_reset;
+
+bit [DATA_BITS-1:0] mem [0:(1<<ADDR_BITS)-1];
+initial $readmemh("mem/mem.hex", mem);
+
+bit rx_ready;
+bit rx_valid;
+bit [7:0] rx_data;
+
+bit tx_ready;
+bit tx_valid;
+bit [7:0] tx_data;
+
+jtag_uart
+    #(  .INSTANCE(0)
+    ) uart0
+    (   .clk(clk)
+    ,   .reset(reset)
+
+    ,   .rx_ready(rx_ready)
+    ,   .rx_valid(rx_valid) `define rx_valid `past(rx_valid)
+    ,   .rx_data(rx_data)   `define rx_data `past(rx_data)
+
+    ,   .tx_ready(tx_ready) `define tx_ready `past(tx_ready)
+    ,   .tx_valid(tx_valid)
+    ,   .tx_data(tx_data)
+    );
+
+bit [DATA_BITS-1:0] pc;
+bit [3:0] opcode;
+bit [7:0] operand;
+bit [DATA_BITS-1:0] acc;
+
+enum
+    {   FETCH
+    ,   DECODE
+    } state;
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        rx_ready = 0;
+        tx_valid = 0;
+        tx_data = 0;
+        pc = 0;
+        acc = 0;
+        state = state.first;
+    end else begin
+        if (`tx_ready) tx_valid = 0;
+
+        case (state)
+            FETCH: begin
+                {opcode, operand} = mem[{2'b0, pc}];
+                ++pc;
+                state = DECODE;
+            end
+
+            DECODE: begin
+                state = FETCH;
+                case (opcode)
+                    'b000: acc = {{4{operand[7]}}, operand};
+                    'b001: begin
+                        if (tx_valid) begin
+                            state = DECODE;
+                        end else begin
+                            tx_valid = 1;
+                            tx_data = acc[7:0];
+                        end
+                    end
+                    'b111: state = DECODE;
+                endcase
+            end
+        endcase
+    end
+end
+
+endmodule
-- 
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