From abd9703a1b96225db0d7317bf8833467150bae26 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Thu, 15 Apr 2021 16:39:58 -0700
Subject: Change synthesis of PLL wrapper to avoid latch logic.

---
 hdl/top.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'hdl/top.sv')

diff --git a/hdl/top.sv b/hdl/top.sv
index 46620cb..0aebd77 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -12,8 +12,8 @@ bit clk;
 bit reset;
 
 clock
-    #(  .DIVIDE_BY(10)
-    ,   .MULTIPLY_BY(9)
+    #(  .MULTIPLY_BY(9)
+    ,   .DIVIDE_BY(10)
     ) pll
     (   .native_clk(native_clk)
     ,   .reset_n(reset_n)
-- 
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