From 6a1c04608090cc8fc88aafac0b4899e4cbb9cae9 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Mon, 5 Apr 2021 10:20:02 -0700
Subject: Change our simulator timing model to use continuous assignment
 guards.

Instead of depending on verilator getting $past right, this (ab-)uses
the SystemVerilog scheduling model which allows us to get a consistent
view of the universe by "isolating" the blocking updates. Easier to code
to and seems to be more reliable in verilator.
---
 hdl/util.svh | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

(limited to 'hdl/util.svh')

diff --git a/hdl/util.svh b/hdl/util.svh
index db5e4e6..fa6ddc5 100644
--- a/hdl/util.svh
+++ b/hdl/util.svh
@@ -1,5 +1,2 @@
-`ifdef SYNTHESIS
-`define past(x) x
-`else
-`define past(x) $sampled(x)
-`endif
+`define input(x) type(x) x``_; assign x``_ = x;
+`define output(x) type(x) x``_; assign x = x``_;
-- 
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