From 11ed7d9b5d90a657ac959b322ae48c2c6916e4e9 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 28 Mar 2021 16:46:55 -0700
Subject: Pessimize JTAG UART somewhat.

---
 hdl/jtag_uart.sv | 4 ++++
 hdl/top.sv       | 9 +--------
 2 files changed, 5 insertions(+), 8 deletions(-)

(limited to 'hdl')

diff --git a/hdl/jtag_uart.sv b/hdl/jtag_uart.sv
index ad4665e..c297811 100644
--- a/hdl/jtag_uart.sv
+++ b/hdl/jtag_uart.sv
@@ -75,7 +75,11 @@ always_ff @(posedge clk) begin
             $write("%s", tx_b_data);
             tx_b_valid = 0;
         end
+`ifdef JTAG_UART_FAST
         tx_ready = !tx_b_valid;
+`else
+        tx_ready = !tx_b_valid && !tx_ready && `tx_valid;
+`endif
     end
 end
 
diff --git a/hdl/top.sv b/hdl/top.sv
index 4f56b1f..c87cc29 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -126,14 +126,7 @@ always_ff @(posedge clk) begin
                         if (operand[3]) --idx;
                         if (operand[4]) {idx, acc} = {acc, idx};
                         if (operand[5]) idx = acc;
-                        if (operand[6]) begin
-                            if (tx_valid) begin
-                                state = MEMORY;
-                            end else begin
-                                tx_valid = 1;
-                                tx_data = acc[7:0];
-                            end
-                        end
+                        if (operand[6]) state = MEMORY;
                         if (operand[7]) state = DECODE;
                     end
                 endcase
-- 
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