From 7a1311c16c36b18a66a5ee43511fb9ad5093ec3a Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 28 Mar 2021 14:48:30 -0700
Subject: Initial commit.

---
 hdl/jtag_uart.sv | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 hdl/top.sv       | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 hdl/util.svh     |  5 ++++
 3 files changed, 178 insertions(+)
 create mode 100644 hdl/jtag_uart.sv
 create mode 100644 hdl/top.sv
 create mode 100644 hdl/util.svh

(limited to 'hdl')

diff --git a/hdl/jtag_uart.sv b/hdl/jtag_uart.sv
new file mode 100644
index 0000000..ad4665e
--- /dev/null
+++ b/hdl/jtag_uart.sv
@@ -0,0 +1,84 @@
+`include "util.svh"
+
+module jtag_uart
+    #(  INSTANCE = 0
+
+    ,   RX_FIFO_BITS = 6
+    ,   TX_FIFO_BITS = 6
+    )
+    (   input   bit clk
+    ,   input   bit reset
+
+    ,   input   bit         rx_ready    `define rx_ready `past(rx_ready)
+    ,   output  bit         rx_valid
+    ,   output  bit [7:0]   rx_data
+
+    ,   output  bit         tx_ready
+    ,   input   bit         tx_valid    `define tx_valid `past(tx_valid)
+    ,   input   bit [7:0]   tx_data     `define tx_data `past(tx_data)
+    );
+
+`ifdef SYNTHESIS
+
+alt_jtag_atlantic
+    #(  .INSTANCE_ID(INSTANCE)
+    ,   .LOG2_RXFIFO_DEPTH(RX_FIFO_BITS)
+    ,   .LOG2_TXFIFO_DEPTH(TX_FIFO_BITS)
+    ,   .SLD_AUTO_INSTANCE_INDEX("NO")
+    ) real_jtag
+    (   .clk(clk)
+    ,   .rst_n(!reset)
+    ,   .r_dat(tx_data)
+    ,   .r_val(tx_valid)
+    ,   .r_ena(tx_ready)
+    ,   .t_dat(rx_data)
+    ,   .t_dav(rx_ready)
+    ,   .t_ena(rx_valid)
+    );
+
+`else
+
+bit [7:0] sim_rx_rom [0:(1<<16)-1];
+initial $readmemh("mem/jtag_uart.hex", sim_rx_rom);
+
+bit [15:0] sim_rx_addr;
+
+bit tx_b_valid;
+bit [7:0] tx_b_data;
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        rx_valid = 0;
+        tx_ready = 0;
+        sim_rx_addr = 0;
+        tx_b_valid = 0;
+    end else begin
+        automatic bit [7:0] sim_rx_data = sim_rx_rom[sim_rx_addr];
+
+        // RX logic
+        if (`rx_ready) rx_valid = 0;
+        if (!rx_valid && (sim_rx_data != 0)) begin
+`ifdef JTAG_UART_LOCAL_ECHO
+            $write("%s", sim_rx_data);
+`endif
+            rx_valid = 1;
+            rx_data = sim_rx_data;
+            ++sim_rx_addr;
+        end
+
+        // TX logic
+        if (tx_ready && `tx_valid) begin
+            tx_b_valid = 1;
+            tx_b_data = `tx_data;
+        end
+        if (tx_b_valid) begin
+            $write("%s", tx_b_data);
+            tx_b_valid = 0;
+        end
+        tx_ready = !tx_b_valid;
+    end
+end
+
+`endif
+
+endmodule
diff --git a/hdl/top.sv b/hdl/top.sv
new file mode 100644
index 0000000..8524b63
--- /dev/null
+++ b/hdl/top.sv
@@ -0,0 +1,89 @@
+`include "util.svh"
+
+module top
+    #(  ADDR_BITS   = 14
+    ,   DATA_BITS   = 12
+    )
+    (   input   bit clk     // verilator public
+    ,   input   bit reset_n // verilator public
+    );
+
+bit reset = 0;
+bit have_reset = 0;
+always_ff @(posedge clk) if (reset) have_reset <= 1;
+assign reset = !reset_n || !have_reset;
+
+bit [DATA_BITS-1:0] mem [0:(1<<ADDR_BITS)-1];
+initial $readmemh("mem/mem.hex", mem);
+
+bit rx_ready;
+bit rx_valid;
+bit [7:0] rx_data;
+
+bit tx_ready;
+bit tx_valid;
+bit [7:0] tx_data;
+
+jtag_uart
+    #(  .INSTANCE(0)
+    ) uart0
+    (   .clk(clk)
+    ,   .reset(reset)
+
+    ,   .rx_ready(rx_ready)
+    ,   .rx_valid(rx_valid) `define rx_valid `past(rx_valid)
+    ,   .rx_data(rx_data)   `define rx_data `past(rx_data)
+
+    ,   .tx_ready(tx_ready) `define tx_ready `past(tx_ready)
+    ,   .tx_valid(tx_valid)
+    ,   .tx_data(tx_data)
+    );
+
+bit [DATA_BITS-1:0] pc;
+bit [3:0] opcode;
+bit [7:0] operand;
+bit [DATA_BITS-1:0] acc;
+
+enum
+    {   FETCH
+    ,   DECODE
+    } state;
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        rx_ready = 0;
+        tx_valid = 0;
+        tx_data = 0;
+        pc = 0;
+        acc = 0;
+        state = state.first;
+    end else begin
+        if (`tx_ready) tx_valid = 0;
+
+        case (state)
+            FETCH: begin
+                {opcode, operand} = mem[{2'b0, pc}];
+                ++pc;
+                state = DECODE;
+            end
+
+            DECODE: begin
+                state = FETCH;
+                case (opcode)
+                    'b000: acc = {{4{operand[7]}}, operand};
+                    'b001: begin
+                        if (tx_valid) begin
+                            state = DECODE;
+                        end else begin
+                            tx_valid = 1;
+                            tx_data = acc[7:0];
+                        end
+                    end
+                    'b111: state = DECODE;
+                endcase
+            end
+        endcase
+    end
+end
+
+endmodule
diff --git a/hdl/util.svh b/hdl/util.svh
new file mode 100644
index 0000000..ddba543
--- /dev/null
+++ b/hdl/util.svh
@@ -0,0 +1,5 @@
+`ifdef SYNTHESIS
+`define past(x) x
+`else
+`define past(x) $past(x)
+`endif
-- 
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