From 9d5484923941eb393381b5769a4f1f66ff5df5ca Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 28 Mar 2021 16:32:13 -0700
Subject: Use a separate memory module.

Hopefully this will infer a memory the way we want in Quartus.
---
 hdl/mem.sv | 30 +++++++++++++++++++++
 hdl/top.sv | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
 2 files changed, 110 insertions(+), 9 deletions(-)
 create mode 100644 hdl/mem.sv

(limited to 'hdl')

diff --git a/hdl/mem.sv b/hdl/mem.sv
new file mode 100644
index 0000000..906870d
--- /dev/null
+++ b/hdl/mem.sv
@@ -0,0 +1,30 @@
+module mem
+    (   input   bit clk
+
+    ,   output  bit                 ready
+    ,   input   bit                 valid
+    ,   input   bit                 write
+    ,   input   bit [ADDR_BITS-1:0] address
+    ,   input   bit [DATA_BITS-1:0] write_data
+    ,   output  bit [DATA_BITS-1:0] read_data   // Valid exactly the cycle after address is consumed.
+    );
+
+parameter ADDR_BITS;
+parameter DATA_BITS;
+parameter INIT_FILE;
+
+bit [DATA_BITS-1:0] storage [0:(1<<ADDR_BITS)-1];
+initial $readmemh(INIT_FILE, storage);
+
+assign ready = 1;
+
+always_ff @(posedge clk) begin
+    if (ready && valid) begin
+        if (write)
+            storage[address] <= write_data;
+        else
+            read_data <= storage[address];
+    end
+end
+
+endmodule
diff --git a/hdl/top.sv b/hdl/top.sv
index aa5a4e2..4f56b1f 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -13,8 +13,28 @@ bit have_reset = 0;
 always_ff @(posedge clk) if (reset) have_reset <= 1;
 assign reset = !reset_n || !have_reset;
 
-bit [DATA_BITS-1:0] mem [0:(1<<ADDR_BITS)-1];
-initial $readmemh("mem/mem.hex", mem);
+bit mem_ready; `define mem_ready `past(mem_ready)
+bit mem_valid;
+bit mem_write;
+bit [ADDR_BITS-1:0] mem_address;
+bit [DATA_BITS-1:0] mem_write_data;
+bit [DATA_BITS-1:0] mem_read_data;
+
+mem
+    #(  .ADDR_BITS(ADDR_BITS)
+    ,   .DATA_BITS(DATA_BITS)
+    ,   .INIT_FILE("mem/mem.hex")
+    )
+    memory
+    (   .clk(clk)
+
+    ,   .ready(mem_ready)
+    ,   .valid(mem_valid)
+    ,   .address(mem_address)
+    ,   .write(mem_write)
+    ,   .write_data(mem_write_data)
+    ,   .read_data(mem_read_data)
+    );
 
 bit rx_ready;
 bit rx_valid;
@@ -48,10 +68,12 @@ bit [DATA_BITS-1:0] idx;
 enum
     {   FETCH
     ,   DECODE
+    ,   MEMORY
     } state;
 
 always_ff @(posedge clk) begin
     if (reset) begin
+        mem_valid = 0;
         rx_ready = 0;
         tx_valid = 0;
         tx_data = 0;
@@ -60,22 +82,41 @@ always_ff @(posedge clk) begin
         idx = 0;
         state = state.first;
     end else begin
+        `ifdef DEBUG $display("s=%0d pc=%x (acc=%x idx=%x)", state, pc, acc, idx); `endif
         if (`tx_ready) tx_valid = 0;
 
         case (state)
             FETCH: begin
-                {opcode, operand} = mem[{2'b0, pc}];
-                ++pc;
-                state = DECODE;
+                `ifdef DEBUG $display("\tfetch"); `endif
+                mem_valid = 1;
+                mem_address = {2'b0, pc};
+                mem_write = 0;
+                if (`mem_ready) begin
+                    state = DECODE;
+                    ++pc;
+                end
             end
 
             DECODE: begin
-                //$display("%x %x:%x (acc=%x idx=%x)", pc, opcode, operand, acc, idx);
+                mem_valid = 0;
+                mem_write = 0;
                 state = FETCH;
+                {opcode, operand} = mem_read_data;
+                `ifdef DEBUG $display("\tdecode %x:%x", opcode, operand); `endif
                 case (opcode)
                     'h0: acc = {{4{operand[7]}}, operand};
-                    'h1: acc = mem[idx + operand];
-                    'h2: mem[idx + operand] = acc;
+                    'h1: begin
+                        mem_valid = 1;
+                        mem_address = idx + operand;
+                        state = MEMORY;
+                    end
+                    'h2: begin
+                        mem_valid = 1;
+                        mem_address = idx + operand;
+                        mem_write = 1;
+                        mem_write_data = acc;
+                        if (! `mem_ready) state = MEMORY;
+                    end
                     'h3: if (acc != operand) ++pc;
                     'h4: pc = pc + {{4{operand[7]}}, operand};
                     'hf: begin
@@ -87,7 +128,7 @@ always_ff @(posedge clk) begin
                         if (operand[5]) idx = acc;
                         if (operand[6]) begin
                             if (tx_valid) begin
-                                state = DECODE;
+                                state = MEMORY;
                             end else begin
                                 tx_valid = 1;
                                 tx_data = acc[7:0];
@@ -97,7 +138,37 @@ always_ff @(posedge clk) begin
                     end
                 endcase
             end
+
+            MEMORY: begin
+                `ifdef DEBUG $display("\tstall"); `endif
+                if (`mem_ready) begin
+                    mem_valid = 0;
+                    mem_write = 0;
+                end
+                state = FETCH;
+                case (opcode)
+                    'h1: begin
+                        if (`mem_ready) begin
+                            acc = mem_read_data;
+                        end else begin
+                            state = MEMORY;
+                        end
+                    end
+                    'hf: begin
+                        if (operand[6]) begin
+                            if (tx_valid) begin
+                                state = MEMORY;
+                            end else begin
+                                tx_valid = 1;
+                                tx_data = acc[7:0];
+                            end
+                        end
+                    end
+                endcase
+            end
         endcase
+
+        `ifdef DEBUG if (mem_valid) $display("\tmem addr=%x w=%b", mem_address, mem_write); `endif
     end
 end
 
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