From e65524eacc977780ca8716951f02d813fdf841ea Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 18 Apr 2021 18:44:08 -0700
Subject: Fix a few trivial errors with vector sizes, state names, and syntax.

---
 hdl/core.sv | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'hdl')

diff --git a/hdl/core.sv b/hdl/core.sv
index 83f4f01..5bee974 100644
--- a/hdl/core.sv
+++ b/hdl/core.sv
@@ -59,7 +59,7 @@ jtag_uart
     ,   .tx_data(tx_data)
     );
 
-bit [ADDR_BITS-1:ADDR_BITS-6] page;
+bit [ADDR_BITS-1:7] page;
 
 bit [ADDR_BITS-1:0] pc;
 bit [2:0] opcode;
@@ -80,7 +80,7 @@ enum
     ,   PREINC
     ,   AGEN
     ,   EXEC
-    ,   STORE
+    ,   MEMWAIT
     ,   HALT
     } state;
 
@@ -104,7 +104,7 @@ always_ff @(posedge clk) begin
                 mem_write = 0;
                 if (`lag(mem_ready)) begin
                     state = DECODE;
-                    page = pc[ADDR_BITS-1:ADDR_BITS-6];
+                    page = pc[ADDR_BITS-1:7];
                     ++pc;
                 end
             end
@@ -169,7 +169,7 @@ always_ff @(posedge clk) begin
                 mem_valid = 1;
                 mem_write = 1;
                 mem_write_data = address[DATA_BITS-1:0];
-                case (opcode) begin
+                case (opcode)
                     'b000, 'b001, 'b010: state = `lag(mem_ready) ? PREINC : AGEN;
                     'b011, 'b100, 'b101: state = `lag(mem_ready) ? PREINC : EXEC;
                 endcase
-- 
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