From 4203007c5ac99c6f46b2aea378d043511b2d798d Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Thu, 15 Apr 2021 16:39:30 -0700
Subject: Fix timing declarations for PLL in Quartus assignments.

---
 tcl/init.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tcl')

diff --git a/tcl/init.tcl b/tcl/init.tcl
index 96ed9de..3466f17 100644
--- a/tcl/init.tcl
+++ b/tcl/init.tcl
@@ -11,7 +11,7 @@ proc pin {loc net} {
     set_instance_assignment -name IO_STANDARD "3.3V LVTTL" -to $net
 }
 
-pin E1  clk
+pin E1  native_clk
 pin J15 reset_n
 
 # This is the clock for timing-driven synthesis, not timing analysis.
-- 
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