SOURCES := $(shell find hdl sim -name \*.sv -o -name \*.cpp)
HEADERS := $(shell find hdl -name \*.svh)
MEMORIES := $(shell find mem -name \*.hex)

OPTS ?=

sim: build/Vtop
	$<
.PHONY: sim

build/Vtop: $(SOURCES) $(HEADERS)
	@rm -rf verilator
	@mkdir -p build verilator
	verilator +1800-2017ext+sv -Wall -Wno-BLKSEQ -Wno-UNUSED -O3 -Ihdl $(OPTS) --Mdir verilator --trace --cc --build -j --exe --top-module top $(SOURCES)
	@ln -t build -f verilator/Vtop
	@rm -rf verilator

noncpu.qpf: $(SOURCES) $(HEADERS) $(MEMORIES)
	quartus_sh -t tcl/init.tcl

noncpu.sof: noncpu.qpf $(SOURCES) $(HEADERS) $(MEMORIES)
	quartus_sh --flow compile $<

fpga: noncpu.sof
	quartus_pgm -c 1 -m JTAG -o "P;$<@1"
	nios2-terminal
.PHONY: fpga

clean:
	git clean -dfX
.PHONY: clean