`include "util.svh"

module jtag_uart
    #(  INSTANCE = 0

    ,   RX_FIFO_BITS = 6
    ,   TX_FIFO_BITS = 6
    )
    (   input   bit clk
    ,   input   bit reset

    ,   input   bit         rx_ready
    ,   output  bit         rx_valid
    ,   output  bit [7:0]   rx_data

    ,   output  bit         tx_ready
    ,   input   bit         tx_valid
    ,   input   bit [7:0]   tx_data
    );

`input(rx_ready)
`output(rx_valid)
`output(rx_data)
`output(tx_ready)
`input(tx_valid)
`input(tx_data)

`ifdef SYNTHESIS

alt_jtag_atlantic
    #(  .INSTANCE_ID(INSTANCE)
    ,   .LOG2_RXFIFO_DEPTH(RX_FIFO_BITS)
    ,   .LOG2_TXFIFO_DEPTH(TX_FIFO_BITS)
    ,   .SLD_AUTO_INSTANCE_INDEX("NO")
    ) real_jtag
    (   .clk(clk)
    ,   .rst_n(!reset)
    ,   .r_dat(tx_data_)
    ,   .r_val(tx_valid_)
    ,   .r_ena(tx_ready_)
    ,   .t_dat(rx_data_)
    ,   .t_dav(rx_ready_)
    ,   .t_ena(rx_valid_)
    );

`else

bit [7:0] sim_rx_rom [0:(1<<16)-1];
initial $readmemh("mem/jtag_uart.hex", sim_rx_rom);

bit [15:0] sim_rx_addr;

bit tx_b_valid;
bit [7:0] tx_b_data;

always_ff @(posedge clk) begin
    if (reset) begin
        rx_valid_ = 0;
        tx_ready_ = 0;
        sim_rx_addr = 0;
        tx_b_valid = 0;
    end else begin
        automatic bit [7:0] sim_rx_data = sim_rx_rom[sim_rx_addr];

        // RX logic
        if (rx_ready_) rx_valid_ = 0;
        if (!rx_valid_ && (sim_rx_data != 0)) begin
`ifdef JTAG_UART_LOCAL_ECHO
            $write("%s", sim_rx_data);
`endif
            rx_valid_ = 1;
            rx_data_ = sim_rx_data;
            ++sim_rx_addr;
        end

        // TX logic
        if (tx_ready_ && tx_valid_) begin
            tx_b_valid = 1;
            tx_b_data = tx_data_;
        end
        if (tx_b_valid) begin
            $write("%s", tx_b_data);
            tx_b_valid = 0;
        end
        tx_ready_ = !tx_b_valid;
    end
end

`endif

endmodule