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SOURCES := $(shell find hdl sim -name \*.sv -o -name \*.cpp)
HEADERS := $(shell find hdl -name \*.svh)
MEMORIES := $(shell find mem -name \*.hex)
QUARTUS := $(shell find altera tcl -name \*.cdf -o -name \*.sdc -o -name \*.tcl)
OPTS ?=
sim: build/Vtop
$<
.PHONY: sim
build/Vtop: $(SOURCES) $(HEADERS)
@rm -rf verilator
@mkdir -p build verilator
verilator +1800-2017ext+sv -Wall -Wno-BLKSEQ -Wno-UNUSED -O3 -Ihdl $(OPTS) --Mdir verilator --trace --cc --build -j --exe --top-module top $(SOURCES)
@ln -t build -f verilator/Vtop
@rm -rf verilator
noncpu.sof: $(SOURCES) $(HEADERS) $(MEMORIES) $(QUARTUS)
[ ! -e noncpu.qpf ] || quartus_sh -t tcl/clean.tcl
quartus_sh -t tcl/init.tcl
quartus_sh --flow compile noncpu.qpf
fpga: noncpu.sof
quartus_pgm -c 1 -m JTAG -o "P;$<@1"
nios2-terminal
.PHONY: fpga
clean:
git clean -dfX
.PHONY: clean
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