hdl/mem.sv


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

`include "util.svh"

module mem
    (   input   bit clk
    ,   input   bit reset

    ,   output  bit                 ready
    ,   input   bit                 valid       `define valid `past(valid)
    ,   input   bit                 write       `define write `past(write)
    ,   input   bit [ADDR_BITS-1:0] address     `define address `past(address)
    ,   input   bit [DATA_BITS-1:0] write_data  `define write_data `past(write_data)

    ,   output  bit                 read_valid
    ,   output  bit [DATA_BITS-1:0] read_data
    );

parameter ADDR_BITS;
parameter DATA_BITS;
parameter INIT_FILE;

bit [DATA_BITS-1:0] storage [0:(1<<ADDR_BITS)-1];
initial $readmemh(INIT_FILE, storage);

always_ff @(posedge clk) begin
    if (reset) begin
        ready = 0;
        read_valid = 0;
    end else begin
        read_valid = 0;
        if (ready && `valid) begin
            if (`write) begin
                storage[`address] = `write_data;
            end else begin
                read_valid = 1;
                read_data = storage[`address];
            end
        end
        ready = 1;
    end
end

endmodule