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|
`include "util.svh"
module mem
( input bit clk
, input bit reset
, output bit ready
, input bit valid
, input bit write
, input bit [ADDR_BITS-1:0] address
, input bit [DATA_BITS-1:0] write_data
, output bit read_valid
, output bit [DATA_BITS-1:0] read_data
);
parameter ADDR_BITS;
parameter DATA_BITS;
parameter INIT_FILE;
bit [DATA_BITS-1:0] storage [0:(1<<ADDR_BITS)-1];
initial $readmemh(INIT_FILE, storage);
always_ff @(posedge clk) begin
if (reset) begin
ready = 0;
read_valid = 0;
end else begin
read_valid = 0;
if (ready && `lag(valid)) begin
if (`lag(write)) begin
storage[`lag(address)] = `lag(write_data);
end else begin
read_valid = 1;
read_data = storage[`lag(address)];
end
end
ready = 1;
end
end
endmodule
|
