hdl/mem.sv


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module mem
    (   input   bit clk

    ,   output  bit                 ready
    ,   input   bit                 valid
    ,   input   bit                 write
    ,   input   bit [ADDR_BITS-1:0] address
    ,   input   bit [DATA_BITS-1:0] write_data
    ,   output  bit [DATA_BITS-1:0] read_data   // Valid exactly the cycle after address is consumed.
    );

parameter ADDR_BITS;
parameter DATA_BITS;
parameter INIT_FILE;

bit [DATA_BITS-1:0] storage [0:(1<<ADDR_BITS)-1];
initial $readmemh(INIT_FILE, storage);

assign ready = 1;

always_ff @(posedge clk) begin
    if (ready && valid) begin
        if (write)
            storage[address] <= write_data;
        else
            read_data <= storage[address];
    end
end

endmodule