hdl/mem.sv


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`include "util.svh"

module mem
    (   input   bit clk
    ,   input   bit reset

    ,   output  bit                 ready
    ,   input   bit                 valid
    ,   input   bit                 write
    ,   input   bit [ADDR_BITS-1:0] address
    ,   input   bit [DATA_BITS-1:0] write_data

    ,   output  bit                 read_valid
    ,   output  bit [DATA_BITS-1:0] read_data
    );

parameter ADDR_BITS;
parameter DATA_BITS;
parameter INIT_FILE;

`output(ready)
`input(valid)
`input(write)
`input(address)
`input(write_data)
`output(read_valid)
`output(read_data)

bit [DATA_BITS-1:0] storage [0:(1<<ADDR_BITS)-1];
initial $readmemh(INIT_FILE, storage);

always_ff @(posedge clk) begin
    if (reset) begin
        ready_ = 0;
        read_valid_ = 0;
    end else begin
        read_valid_ = 0;
        if (ready_ && valid_) begin
            if (write_) begin
                storage[address_] = write_data_;
            end else begin
                read_valid_ = 1;
                read_data_ = storage[address_];
            end
        end
        ready_ = 1;
    end
end

endmodule