hdl/top.sv


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`include "util.svh"

module top
    (   input   bit native_clk  // verilator public
    ,   input   bit reset_n     // verilator public
    );

bit clk;
bit reset;

clock
    #(  .MULTIPLY_BY(9)
    ,   .DIVIDE_BY(10)
    ) pll
    (   .native_clk(native_clk)
    ,   .reset_n(reset_n)
    ,   .target_clk(clk)
    ,   .reset(reset)
    );

core cpu
    (   .clk(clk)
    ,   .reset(reset)
    );

endmodule