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| author | Julian Blake Kongslie | 2022-02-16 14:44:01 -0800 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-02-16 14:44:01 -0800 |
| commit | 92420e248d4449a2aa61e92f05c0867912d48d56 (patch) | |
| tree | 889d0af684d648713cd1ae68b5b2c550d2b6dc7f /hdl/echo_arbiter.sv | |
| parent | Complete rewrite to break out the separate state machines and fix timing (diff) | |
| download | simple-memory-controller-92420e248d4449a2aa61e92f05c0867912d48d56.tar.xz | |
Split into multiple files.
Diffstat (limited to '')
| -rw-r--r-- | hdl/echo_arbiter.sv | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/hdl/echo_arbiter.sv b/hdl/echo_arbiter.sv new file mode 100644 index 0000000..b6892b1 --- /dev/null +++ b/hdl/echo_arbiter.sv | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | module echo_arbiter | ||
| 2 | ( input bit clock | ||
| 3 | , input bit resetn | ||
| 4 | |||
| 5 | , output bit in0_ready | ||
| 6 | , input bit in0_valid | ||
| 7 | , input bit [7:0] in0_data | ||
| 8 | |||
| 9 | , output bit in1_ready | ||
| 10 | , input bit in1_valid | ||
| 11 | , input bit [7:0] in1_data | ||
| 12 | |||
| 13 | , input bit out_ready | ||
| 14 | , output bit out_valid | ||
| 15 | , output bit [7:0] out_data | ||
| 16 | ); | ||
| 17 | |||
| 18 | bit in0_hold_valid; | ||
| 19 | bit [7:0] in0_hold; | ||
| 20 | |||
| 21 | bit in1_hold_valid; | ||
| 22 | bit [7:0] in1_hold; | ||
| 23 | |||
| 24 | always @(posedge clock) begin | ||
| 25 | if (!resetn) begin | ||
| 26 | in0_ready = 0; | ||
| 27 | in1_ready = 0; | ||
| 28 | out_valid = 0; | ||
| 29 | out_data = 0; | ||
| 30 | in0_hold_valid = 0; | ||
| 31 | in0_hold = 0; | ||
| 32 | in1_hold_valid = 0; | ||
| 33 | in1_hold = 0; | ||
| 34 | end else begin | ||
| 35 | if (out_ready) out_valid = 0; | ||
| 36 | if (in0_ready && in0_valid) begin | ||
| 37 | in0_hold_valid = 1; | ||
| 38 | in0_hold = in0_data; | ||
| 39 | end | ||
| 40 | if (in1_ready && in1_valid) begin | ||
| 41 | in1_hold_valid = 1; | ||
| 42 | in1_hold = in1_data; | ||
| 43 | end | ||
| 44 | |||
| 45 | if (!out_valid) begin | ||
| 46 | if (in0_hold_valid) begin | ||
| 47 | out_valid = 1; | ||
| 48 | out_data = in0_hold; | ||
| 49 | in0_hold_valid = 0; | ||
| 50 | end else if (in1_hold_valid) begin | ||
| 51 | out_valid = 1; | ||
| 52 | out_data = in1_hold; | ||
| 53 | in1_hold_valid = 0; | ||
| 54 | end | ||
| 55 | end | ||
| 56 | |||
| 57 | in0_ready = !in0_hold_valid; | ||
| 58 | in1_ready = !in1_hold_valid; | ||
| 59 | end | ||
| 60 | end | ||
| 61 | |||
| 62 | endmodule | ||
