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| author | Julian Blake Kongslie | 2022-02-20 15:25:50 -0800 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-02-20 15:25:50 -0800 |
| commit | 75410a2a7f0abb8677c1e03bfe2238923219aa46 (patch) | |
| tree | 81fea2837594bb41db986cb746a245df84383ce8 /hdl/ram_controller.sv | |
| parent | SignalTap bullshit. (diff) | |
| download | simple-memory-controller-75410a2a7f0abb8677c1e03bfe2238923219aa46.tar.xz | |
CSn[0] is, in fact, a lie. We only have 23 bits of address space.
Diffstat (limited to '')
| -rw-r--r-- | hdl/ram_controller.sv | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/hdl/ram_controller.sv b/hdl/ram_controller.sv index 44d200b..d32560d 100644 --- a/hdl/ram_controller.sv +++ b/hdl/ram_controller.sv | |||
| @@ -4,7 +4,7 @@ module ram_controller | |||
| 4 | 4 | ||
| 5 | , output bit command_ready | 5 | , output bit command_ready |
| 6 | , input bit command_valid | 6 | , input bit command_valid |
| 7 | , input bit [23:0] command_address | 7 | , input bit [22:0] command_address |
| 8 | , input bit command_write | 8 | , input bit command_write |
| 9 | , input bit [15:0] command_data | 9 | , input bit [15:0] command_data |
| 10 | 10 | ||
| @@ -13,7 +13,7 @@ module ram_controller | |||
| 13 | , output bit [15:0] result_data | 13 | , output bit [15:0] result_data |
| 14 | 14 | ||
| 15 | , output bit ram_resetn | 15 | , output bit ram_resetn |
| 16 | , output bit [1:0] ram_csn | 16 | , output bit ram_csn |
| 17 | , output bit ram_clkp | 17 | , output bit ram_clkp |
| 18 | , output bit ram_clkn | 18 | , output bit ram_clkn |
| 19 | , output bit ram_rwds_oe | 19 | , output bit ram_rwds_oe |
| @@ -27,7 +27,7 @@ module ram_controller | |||
| 27 | assign ram_clkn = !ram_clkp; | 27 | assign ram_clkn = !ram_clkp; |
| 28 | 28 | ||
| 29 | bit valid; | 29 | bit valid; |
| 30 | bit [23:0] address; | 30 | bit [22:0] address; |
| 31 | bit write; | 31 | bit write; |
| 32 | bit [15:0] data; | 32 | bit [15:0] data; |
| 33 | 33 | ||
| @@ -77,16 +77,22 @@ module ram_controller | |||
| 77 | , DATA_2 | 77 | , DATA_2 |
| 78 | } state; | 78 | } state; |
| 79 | 79 | ||
| 80 | (* syn_encoding = "compact" *) enum bit | ||
| 81 | { SETUP_OUTPUTS | ||
| 82 | , TOGGLE_CLOCK | ||
| 83 | } half_state; | ||
| 84 | |||
| 80 | bit [2:0] reset_counter; | 85 | bit [2:0] reset_counter; |
| 81 | 86 | ||
| 87 | bit prev_rwds; | ||
| 88 | |||
| 82 | always @(posedge clock) begin | 89 | always @(posedge clock) begin |
| 83 | if (!resetn || reset_counter != 0) begin | 90 | if (!resetn || reset_counter != 0) begin |
| 84 | command_ready = 0; | 91 | command_ready = 0; |
| 85 | result_valid = 0; | 92 | result_valid = 0; |
| 86 | result_data = 0; | 93 | result_data = 0; |
| 87 | ram_resetn = 0; | 94 | ram_resetn = 0; |
| 88 | ram_csn[0] = 1; | 95 | ram_csn = 1; |
| 89 | ram_csn[1] = 1; | ||
| 90 | ram_clkp = 0; | 96 | ram_clkp = 0; |
| 91 | ram_rwds_oe = 0; | 97 | ram_rwds_oe = 0; |
| 92 | ram_rwds_out = 0; | 98 | ram_rwds_out = 0; |
| @@ -117,8 +123,7 @@ module ram_controller | |||
| 117 | end | 123 | end |
| 118 | 124 | ||
| 119 | if (!valid) begin | 125 | if (!valid) begin |
| 120 | ram_csn[0] = 1; | 126 | ram_csn = 1; |
| 121 | ram_csn[1] = 1; | ||
| 122 | ram_clkp = 0; | 127 | ram_clkp = 0; |
| 123 | end else begin | 128 | end else begin |
| 124 | automatic bit stall = 0; | 129 | automatic bit stall = 0; |
| @@ -127,11 +132,10 @@ module ram_controller | |||
| 127 | 132 | ||
| 128 | CHIP_SELECT: begin | 133 | CHIP_SELECT: begin |
| 129 | ram_clkp = 0; // Overriding clock to guarantee that we're starting the command with the correct clock polarity | 134 | ram_clkp = 0; // Overriding clock to guarantee that we're starting the command with the correct clock polarity |
| 130 | ram_csn[address[23]] = 0; | 135 | ram_csn = 0; |
| 131 | end | 136 | end |
| 132 | 137 | ||
| 133 | SEND_COMMAND_1: begin | 138 | SEND_COMMAND_1: begin |
| 134 | ram_csn[address[23]] = 0; | ||
| 135 | ram_data_oe = 1; | 139 | ram_data_oe = 1; |
| 136 | ram_data_out = {!write, 1'b0, 1'b0, 5'b0}; // R/W#, ADDRSPACE, BURST, RESERVED | 140 | ram_data_out = {!write, 1'b0, 1'b0, 5'b0}; // R/W#, ADDRSPACE, BURST, RESERVED |
| 137 | end | 141 | end |
