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| author | Julian Blake Kongslie | 2022-02-17 08:37:06 -0800 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-02-17 08:37:06 -0800 |
| commit | 3f0e2335d93038bd5a71f9de4182c6d0f818ba15 (patch) | |
| tree | a6d378c47f3912102d832cde1d40edfa92402b3a /tcl/init.tcl | |
| parent | Add signal tap for debug. (diff) | |
| download | simple-memory-controller-3f0e2335d93038bd5a71f9de4182c6d0f818ba15.tar.xz | |
Avoid a few warnings during build.
Diffstat (limited to '')
| -rw-r--r-- | tcl/init.tcl | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tcl/init.tcl b/tcl/init.tcl index 82a1697..103a31a 100644 --- a/tcl/init.tcl +++ b/tcl/init.tcl | |||
| @@ -5,6 +5,7 @@ set_global_assignment -name DEVICE 10CL025YU256I7G | |||
| 5 | set_global_assignment -name TOP_LEVEL_ENTITY top | 5 | set_global_assignment -name TOP_LEVEL_ENTITY top |
| 6 | set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 | 6 | set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 |
| 7 | set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1" | 7 | set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1" |
| 8 | set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 | ||
| 8 | 9 | ||
| 9 | proc pin {net loc} { | 10 | proc pin {net loc} { |
| 10 | set_location_assignment -to $net "PIN_$loc" | 11 | set_location_assignment -to $net "PIN_$loc" |