diff options
| author | Julian Blake Kongslie | 2022-02-17 08:36:44 -0800 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-02-17 08:36:44 -0800 |
| commit | b71214c957e427f1405ff336d5c6e4fc16a61475 (patch) | |
| tree | 49980549cc4f7ba97f1c3f62a627c74a1c3df6e9 /tcl | |
| parent | Reorganize controller state machine and tweak timing slightly. (diff) | |
| download | simple-memory-controller-b71214c957e427f1405ff336d5c6e4fc16a61475.tar.xz | |
Add signal tap for debug.
Diffstat (limited to '')
| -rw-r--r-- | tcl/init.tcl | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tcl/init.tcl b/tcl/init.tcl index e2aca53..82a1697 100644 --- a/tcl/init.tcl +++ b/tcl/init.tcl | |||
| @@ -91,6 +91,8 @@ proc add_dir {dir} { | |||
| 91 | add_files CDF cdf $dir | 91 | add_files CDF cdf $dir |
| 92 | add_files HEX hex $dir | 92 | add_files HEX hex $dir |
| 93 | add_files SDC sdc $dir | 93 | add_files SDC sdc $dir |
| 94 | add_files USE_SIGNALTAP stp $dir | ||
| 95 | add_files SIGNALTAP stp $dir | ||
| 94 | add_files VERILOG sv $dir | 96 | add_files VERILOG sv $dir |
| 95 | add_files VERILOG svh $dir | 97 | add_files VERILOG svh $dir |
| 96 | 98 | ||