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-rw-r--r--hdl/command_parser.sv102
-rw-r--r--hdl/echo_arbiter.sv62
-rw-r--r--hdl/ram_controller.sv193
-rw-r--r--hdl/result_printer.sv55
-rw-r--r--hdl/top.sv454
5 files changed, 438 insertions, 428 deletions
diff --git a/hdl/command_parser.sv b/hdl/command_parser.sv
new file mode 100644
index 0000000..d6775ad
--- /dev/null
+++ b/hdl/command_parser.sv
@@ -0,0 +1,102 @@
1module command_parser
2 ( input bit clock
3 , input bit resetn
4
5 , output bit uart_ready
6 , input bit uart_valid
7 , input bit [7:0] uart_data
8
9 , input bit echo_ready
10 , output bit echo_valid
11 , output bit [7:0] echo_data
12
13 , input bit command_ready
14 , output bit command_valid
15 , output bit [23:0] command_address
16 , output bit command_write
17 , output bit [15:0] command_data
18 );
19
20 bit input_byte_valid;
21 bit [7:0] input_byte;
22
23 enum
24 { READ_ADDRESS_OR_COMMAND
25 , READ_DATA_1
26 , READ_DATA_2
27 , READ_DATA_3
28 , READ_DATA_4
29 } state;
30
31 always @(posedge clock) begin
32 if (!resetn) begin
33 uart_ready = 0;
34 command_valid = 0;
35 command_address = 0;
36 command_write = 0;
37 command_data = 0;
38 input_byte_valid = 0;
39 input_byte = 0;
40 state = state.first;
41 end else begin
42 if (echo_ready) echo_valid = 0;
43 if (command_ready) command_valid = 0;
44 if (uart_ready && uart_valid) begin
45 echo_valid = 1;
46 echo_data = uart_data;
47 input_byte_valid = 1;
48 input_byte = uart_data;
49 end
50
51 if (!command_valid && input_byte_valid) begin
52 case (state)
53
54 READ_ADDRESS_OR_COMMAND: begin
55 if (input_byte >= "0" && input_byte <= "9") begin
56 command_address = command_address << 4;
57 command_address[3:0] = input_byte - "0";
58 end else if (input_byte >= "a" && input_byte <= "f") begin
59 command_address = command_address << 4;
60 command_address[3:0] = input_byte - "a" + 10;
61 end else if (input_byte >= "A" && input_byte <= "F") begin
62 command_address = command_address << 4;
63 command_address[3:0] = input_byte - "A" + 10;
64 end else if (input_byte == "?") begin
65 command_valid = 1;
66 command_write = 0;
67 command_data = 0;
68 end else if (input_byte == "=") begin
69 command_write = 1;
70 command_data = 0;
71 state = READ_DATA_1;
72 end
73 end
74
75 READ_DATA_1, READ_DATA_2, READ_DATA_3, READ_DATA_4: begin
76 if (input_byte >= "0" && input_byte <= "9") begin
77 command_data = command_data << 4;
78 command_data[3:0] = input_byte - "0";
79 state = state.next;
80 end else if (input_byte >= "a" && input_byte <= "f") begin
81 command_data = command_data << 4;
82 command_data[3:0] = input_byte - "a" + 10;
83 state = state.next;
84 end else if (input_byte >= "A" && input_byte <= "F") begin
85 command_data = command_data << 4;
86 command_data[3:0] = input_byte - "A" + 10;
87 state = state.next;
88 end else begin
89 state = state.first;
90 end
91 command_valid = state == state.first;
92 end
93
94 endcase
95 input_byte_valid = 0;
96 end
97
98 uart_ready = !echo_valid && !input_byte_valid;
99 end
100 end
101
102endmodule
diff --git a/hdl/echo_arbiter.sv b/hdl/echo_arbiter.sv
new file mode 100644
index 0000000..b6892b1
--- /dev/null
+++ b/hdl/echo_arbiter.sv
@@ -0,0 +1,62 @@
1module echo_arbiter
2 ( input bit clock
3 , input bit resetn
4
5 , output bit in0_ready
6 , input bit in0_valid
7 , input bit [7:0] in0_data
8
9 , output bit in1_ready
10 , input bit in1_valid
11 , input bit [7:0] in1_data
12
13 , input bit out_ready
14 , output bit out_valid
15 , output bit [7:0] out_data
16 );
17
18 bit in0_hold_valid;
19 bit [7:0] in0_hold;
20
21 bit in1_hold_valid;
22 bit [7:0] in1_hold;
23
24 always @(posedge clock) begin
25 if (!resetn) begin
26 in0_ready = 0;
27 in1_ready = 0;
28 out_valid = 0;
29 out_data = 0;
30 in0_hold_valid = 0;
31 in0_hold = 0;
32 in1_hold_valid = 0;
33 in1_hold = 0;
34 end else begin
35 if (out_ready) out_valid = 0;
36 if (in0_ready && in0_valid) begin
37 in0_hold_valid = 1;
38 in0_hold = in0_data;
39 end
40 if (in1_ready && in1_valid) begin
41 in1_hold_valid = 1;
42 in1_hold = in1_data;
43 end
44
45 if (!out_valid) begin
46 if (in0_hold_valid) begin
47 out_valid = 1;
48 out_data = in0_hold;
49 in0_hold_valid = 0;
50 end else if (in1_hold_valid) begin
51 out_valid = 1;
52 out_data = in1_hold;
53 in1_hold_valid = 0;
54 end
55 end
56
57 in0_ready = !in0_hold_valid;
58 in1_ready = !in1_hold_valid;
59 end
60 end
61
62endmodule
diff --git a/hdl/ram_controller.sv b/hdl/ram_controller.sv
new file mode 100644
index 0000000..b6e744b
--- /dev/null
+++ b/hdl/ram_controller.sv
@@ -0,0 +1,193 @@
1module ram_controller
2 ( input bit clock
3 , input bit resetn
4
5 , output bit command_ready
6 , input bit command_valid
7 , input bit [23:0] command_address
8 , input bit command_write
9 , input bit [15:0] command_data
10
11 , input bit result_ready
12 , output bit result_valid
13 , output bit [15:0] result_data
14
15 , output bit ram_resetn
16 , output bit [1:0] ram_csn
17 , output bit ram_clkp
18 , output bit ram_clkn
19 , output bit ram_rwds_oe
20 , input bit ram_rwds_in
21 , output bit ram_rwds_out
22 , output bit ram_data_oe
23 , input bit [7:0] ram_data_in
24 , output bit [7:0] ram_data_out
25 );
26
27 assign ram_clkn = !ram_clkp;
28
29 bit valid;
30 bit [23:0] address;
31 bit write;
32 bit [15:0] data;
33
34 bit slow;
35
36 enum
37 { SEND_COMMAND_1
38 , SEND_COMMAND_2
39 , SEND_COMMAND_3
40 , SEND_COMMAND_4
41 , SEND_COMMAND_5
42 , SEND_COMMAND_6
43
44 , LAT2_CYC1
45 , LAT2_CYC2
46 , LAT2_CYC3
47 , LAT2_CYC4
48 , LAT2_CYC5
49 , LAT2_CYC6
50
51 , LAT1_CYC1
52 , LAT1_CYC2
53 , LAT1_CYC3
54 , LAT1_CYC4
55 // Latency blocks are 6 cycle, but they start in the SEND_COMMAND_5 cycle, so block 1 is only 4 real cycles
56 //, LAT1_CYC5
57 //, LAT1_CYC6
58
59 , DATA_1
60 , DATA_2
61 } state;
62
63 int reset_counter;
64
65 always @(posedge clock) begin
66 if (!resetn || reset_counter != 0) begin
67 command_ready = 0;
68 result_valid = 0;
69 result_data = 0;
70 ram_resetn = 0;
71 ram_csn[0] = 1;
72 ram_csn[1] = 1;
73 ram_clkp = 0;
74 ram_rwds_oe = 0;
75 ram_rwds_out = 0;
76 ram_data_oe = 0;
77 ram_data_out = 0;
78 valid = 0;
79 address = 0;
80 write = 0;
81 data = 0;
82 slow = 0;
83 state = state.first;
84 if (!resetn)
85 reset_counter = 5; // Spec wants >= 100ns of reset
86 else
87 reset_counter = reset_counter - 1;
88 end else begin
89 ram_resetn = 1;
90 ram_rwds_oe = 0;
91 ram_data_oe = 0;
92
93 if (result_ready) result_valid = 0;
94 if (command_ready && command_valid) begin
95 valid = 1;
96 address = command_address;
97 write = command_write;
98 data = command_data;
99 state = state.first;
100 end
101
102 if (!valid) begin
103 ram_csn[0] = 1;
104 ram_csn[1] = 1;
105 ram_clkp = 0;
106 end else begin
107 case (state)
108
109 SEND_COMMAND_1: begin
110 ram_clkp = 0;
111 ram_csn[address[23]] = 0;
112 ram_data_oe = 1;
113 ram_data_out = {!write, 1'b0, 1'b0, 5'b0}; // R/W# AS BURST RESERVED
114 state = state.next;
115 end
116
117 SEND_COMMAND_2: begin
118 ram_clkp = 1;
119 ram_data_oe = 1;
120 ram_data_out = {4'b0, address[22:19]}; // RESERVED ROW
121 state = state.next;
122 end
123
124 SEND_COMMAND_3: begin
125 ram_clkp = 0;
126 ram_data_oe = 1;
127 ram_data_out = {address[18:11]}; // ROW
128 state = state.next;
129 end
130
131 SEND_COMMAND_4: begin
132 ram_clkp = 1;
133 ram_data_oe = 1;
134 ram_data_out = {address[10:9], address[8:3]}; // ROW UPPERCOL
135 slow = ram_rwds_in; // Sort of arbitrarily capturing RWDS in the middle of the command string
136 state = state.next;
137 end
138
139 SEND_COMMAND_5: begin
140 ram_clkp = 0;
141 ram_data_oe = 1;
142 ram_data_out = {8'b0}; // RESERVED
143 state = state.next;
144 end
145
146 SEND_COMMAND_6: begin
147 ram_clkp = 1;
148 ram_data_oe = 1;
149 ram_data_out = {5'b0, address[2:0]}; // RESERVED LOWERCOL
150 if (slow)
151 state = LAT2_CYC1;
152 else
153 state = LAT1_CYC1;
154 end
155
156 LAT2_CYC1, LAT2_CYC2, LAT2_CYC3, LAT2_CYC4, LAT2_CYC5, LAT2_CYC6,
157 LAT1_CYC1, LAT1_CYC2, LAT1_CYC3, LAT1_CYC4: begin
158 ram_clkp = !ram_clkp;
159 state = state.next;
160 end
161
162 DATA_1, DATA_2: begin
163 ram_clkp = !ram_clkp;
164 if (write) begin
165 ram_rwds_oe = 1;
166 ram_rwds_out = 1;
167 ram_data_oe = 1;
168 ram_data_out = data[7:0];
169 data = data >> 8;
170 state = state.next;
171 end else if (ram_rwds_in) begin
172 data = data << 8;
173 data[7:0] = ram_data_in;
174 state = state.next;
175 end
176 end
177
178 endcase
179 if (state == state.first) begin
180 valid = 0;
181 if (!write) begin
182 // We know that this is safe because we don't accept commands unless we have result bandwidth
183 result_valid = 1;
184 result_data = data;
185 end
186 end
187 end
188
189 command_ready = !valid && !result_valid;
190 end
191 end
192
193endmodule
diff --git a/hdl/result_printer.sv b/hdl/result_printer.sv
new file mode 100644
index 0000000..7bcaf31
--- /dev/null
+++ b/hdl/result_printer.sv
@@ -0,0 +1,55 @@
1module result_printer
2 ( input bit clock
3 , input bit resetn
4
5 , output bit result_ready
6 , input bit result_valid
7 , input bit [15:0] result_data
8
9 , input bit echo_ready
10 , output bit echo_valid
11 , output bit [7:0] echo_data
12 );
13
14 bit hold_valid;
15 bit [15:0] hold;
16
17 enum
18 { DIGIT_1
19 , DIGIT_2
20 , DIGIT_3
21 , DIGIT_4
22 } state;
23
24 always @(posedge clock) begin
25 if (!resetn) begin
26 result_ready = 0;
27 echo_valid = 0;
28 echo_data = 0;
29 hold_valid = 0;
30 hold = 0;
31 state = state.first;
32 end else begin
33 if (echo_ready) echo_valid = 0;
34 if (result_ready && result_valid) begin
35 hold_valid = 1;
36 hold = result_data;
37 end
38
39 if (hold_valid && !echo_valid) begin
40 echo_valid = 1;
41 echo_data = hold[15:12];
42 hold = hold << 4;
43 if (echo_data < 10)
44 echo_data = echo_data + "0";
45 else
46 echo_data = echo_data + "A" - 10;
47 state = state.next;
48 if (state == state.first) hold_valid = 0;
49 end
50
51 result_ready = !hold_valid;
52 end
53 end
54
55endmodule
diff --git a/hdl/top.sv b/hdl/top.sv
index fee1b68..d765beb 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -1,405 +1,3 @@
1module command_parser
2 ( input bit clock
3 , input bit resetn
4
5 , output bit uart_ready
6 , input bit uart_valid
7 , input bit [7:0] uart_data
8
9 , input bit echo_ready
10 , output bit echo_valid
11 , output bit [7:0] echo_data
12
13 , input bit command_ready
14 , output bit command_valid
15 , output bit [23:0] command_address
16 , output bit command_write
17 , output bit [15:0] command_data
18 );
19
20 bit input_byte_valid;
21 bit [7:0] input_byte;
22
23 enum
24 { READ_ADDRESS_OR_COMMAND
25 , READ_DATA_1
26 , READ_DATA_2
27 , READ_DATA_3
28 , READ_DATA_4
29 } state;
30
31 always @(posedge clock) begin
32 if (!resetn) begin
33 uart_ready = 0;
34 command_valid = 0;
35 command_address = 0;
36 command_write = 0;
37 command_data = 0;
38 input_byte_valid = 0;
39 input_byte = 0;
40 state = state.first;
41 end else begin
42 if (echo_ready) echo_valid = 0;
43 if (command_ready) command_valid = 0;
44 if (uart_ready && uart_valid) begin
45 echo_valid = 1;
46 echo_data = uart_data;
47 input_byte_valid = 1;
48 input_byte = uart_data;
49 end
50
51 if (!command_valid && input_byte_valid) begin
52 case (state)
53 READ_ADDRESS_OR_COMMAND: begin
54 if (input_byte >= "0" && input_byte <= "9") begin
55 command_address = command_address << 4;
56 command_address[3:0] = input_byte - "0";
57 end else if (input_byte >= "a" && input_byte <= "f") begin
58 command_address = command_address << 4;
59 command_address[3:0] = input_byte - "a" + 10;
60 end else if (input_byte >= "A" && input_byte <= "F") begin
61 command_address = command_address << 4;
62 command_address[3:0] = input_byte - "A" + 10;
63 end else if (input_byte == "?") begin
64 command_valid = 1;
65 command_write = 0;
66 command_data = 0;
67 end else if (input_byte == "=") begin
68 command_write = 1;
69 command_data = 0;
70 state = READ_DATA_1;
71 end
72 end
73 READ_DATA_1, READ_DATA_2, READ_DATA_3, READ_DATA_4: begin
74 if (input_byte >= "0" && input_byte <= "9") begin
75 command_data = command_data << 4;
76 command_data[3:0] = input_byte - "0";
77 state = state.next;
78 end else if (input_byte >= "a" && input_byte <= "f") begin
79 command_data = command_data << 4;
80 command_data[3:0] = input_byte - "a" + 10;
81 state = state.next;
82 end else if (input_byte >= "A" && input_byte <= "F") begin
83 command_data = command_data << 4;
84 command_data[3:0] = input_byte - "A" + 10;
85 state = state.next;
86 end else begin
87 state = state.first;
88 end
89 command_valid = state == state.first;
90 end
91 endcase
92 input_byte_valid = 0;
93 end
94
95 uart_ready = !echo_valid && !input_byte_valid;
96 end
97 end
98
99endmodule
100
101module echo_arbiter
102 ( input bit clock
103 , input bit resetn
104
105 , output bit in0_ready
106 , input bit in0_valid
107 , input bit [7:0] in0_data
108
109 , output bit in1_ready
110 , input bit in1_valid
111 , input bit [7:0] in1_data
112
113 , input bit out_ready
114 , output bit out_valid
115 , output bit [7:0] out_data
116 );
117
118 bit in0_hold_valid;
119 bit [7:0] in0_hold;
120
121 bit in1_hold_valid;
122 bit [7:0] in1_hold;
123
124 always @(posedge clock) begin
125 if (!resetn) begin
126 in0_ready = 0;
127 in1_ready = 0;
128 out_valid = 0;
129 out_data = 0;
130 in0_hold_valid = 0;
131 in0_hold = 0;
132 in1_hold_valid = 0;
133 in1_hold = 0;
134 end else begin
135 if (out_ready) out_valid = 0;
136 if (in0_ready && in0_valid) begin
137 in0_hold_valid = 1;
138 in0_hold = in0_data;
139 end
140 if (in1_ready && in1_valid) begin
141 in1_hold_valid = 1;
142 in1_hold = in1_data;
143 end
144
145 if (!out_valid) begin
146 if (in0_hold_valid) begin
147 out_valid = 1;
148 out_data = in0_hold;
149 in0_hold_valid = 0;
150 end else if (in1_hold_valid) begin
151 out_valid = 1;
152 out_data = in1_hold;
153 in1_hold_valid = 0;
154 end
155 end
156
157 in0_ready = !in0_hold_valid;
158 in1_ready = !in1_hold_valid;
159 end
160 end
161
162endmodule
163
164module ram_controller
165 ( input bit clock
166 , input bit resetn
167
168 , output bit command_ready
169 , input bit command_valid
170 , input bit [23:0] command_address
171 , input bit command_write
172 , input bit [15:0] command_data
173
174 , input bit result_ready
175 , output bit result_valid
176 , output bit [15:0] result_data
177
178 , output bit ram_resetn
179 , output bit [1:0] ram_csn
180 , output bit ram_clkp
181 , output bit ram_clkn
182 , output bit ram_rwds_oe
183 , input bit ram_rwds_in
184 , output bit ram_rwds_out
185 , output bit ram_data_oe
186 , input bit [7:0] ram_data_in
187 , output bit [7:0] ram_data_out
188 );
189
190 assign ram_clkn = !ram_clkp;
191
192 bit valid;
193 bit [23:0] address;
194 bit write;
195 bit [15:0] data;
196
197 int reset_counter;
198
199 bit slow;
200
201 enum
202 { SEND_COMMAND_1
203 , SEND_COMMAND_2
204 , SEND_COMMAND_3
205 , SEND_COMMAND_4
206 , SEND_COMMAND_5
207 , SEND_COMMAND_6
208
209 , LAT2_CYC1
210 , LAT2_CYC2
211 , LAT2_CYC3
212 , LAT2_CYC4
213 , LAT2_CYC5
214 , LAT2_CYC6
215
216 , LAT1_CYC1
217 , LAT1_CYC2
218 , LAT1_CYC3
219 , LAT1_CYC4
220 // Latency blocks are 6 cycle, but they start in the SEND_COMMAND_5 cycle, so block 1 is only 4 real cycles
221 //, LAT1_CYC5
222 //, LAT1_CYC6
223
224 , DATA_1
225 , DATA_2
226 } state;
227
228 always @(posedge clock) begin
229 if (!resetn || reset_counter != 0) begin
230 command_ready = 0;
231 result_valid = 0;
232 result_data = 0;
233 ram_resetn = 0;
234 ram_csn[0] = 1;
235 ram_csn[1] = 1;
236 ram_clkp = 0;
237 ram_rwds_oe = 0;
238 ram_rwds_out = 0;
239 ram_data_oe = 0;
240 ram_data_out = 0;
241 valid = 0;
242 address = 0;
243 write = 0;
244 data = 0;
245 if (!resetn)
246 reset_counter = 5; // Spec wants >= 100ns of reset
247 else
248 reset_counter = reset_counter - 1;
249 slow = 0;
250 state = state.first;
251 end else begin
252 ram_resetn = 1;
253 ram_rwds_oe = 0;
254 ram_data_oe = 0;
255 if (result_ready) result_valid = 0;
256 if (command_ready && command_valid) begin
257 valid = 1;
258 address = command_address;
259 write = command_write;
260 data = command_data;
261 state = state.first;
262 end
263
264 if (!valid) begin
265 ram_csn[0] = 1;
266 ram_csn[1] = 1;
267 ram_clkp = 0;
268 end else begin
269 case (state)
270 SEND_COMMAND_1: begin
271 ram_clkp = 0;
272 ram_csn[address[23]] = 0;
273 ram_data_oe = 1;
274 ram_data_out = {!write, 1'b0, 1'b0, 5'b0}; // R/W# AS BURST RESERVED
275 state = state.next;
276 end
277 SEND_COMMAND_2: begin
278 ram_clkp = 1;
279 ram_data_oe = 1;
280 ram_data_out = {4'b0, address[22:19]}; // RESERVED ROW
281 state = state.next;
282 end
283 SEND_COMMAND_3: begin
284 ram_clkp = 0;
285 ram_data_oe = 1;
286 ram_data_out = {address[18:11]}; // ROW
287 state = state.next;
288 end
289 SEND_COMMAND_4: begin
290 ram_clkp = 1;
291 ram_data_oe = 1;
292 ram_data_out = {address[10:9], address[8:3]}; // ROW UPPERCOL
293 slow = ram_rwds_in; // Sort of arbitrarily capturing RWDS in the middle of the command string
294 state = state.next;
295 end
296 SEND_COMMAND_5: begin
297 ram_clkp = 0;
298 ram_data_oe = 1;
299 ram_data_out = {8'b0}; // RESERVED
300 state = state.next;
301 end
302 SEND_COMMAND_6: begin
303 ram_clkp = 1;
304 ram_data_oe = 1;
305 ram_data_out = {5'b0, address[2:0]}; // RESERVED LOWERCOL
306 if (slow)
307 state = LAT2_CYC1;
308 else
309 state = LAT1_CYC1;
310 end
311 LAT2_CYC1, LAT2_CYC2, LAT2_CYC3, LAT2_CYC4, LAT2_CYC5, LAT2_CYC6,
312 LAT1_CYC1, LAT1_CYC2, LAT1_CYC3, LAT1_CYC4: begin
313 ram_clkp = !ram_clkp;
314 state = state.next;
315 end
316 DATA_1, DATA_2: begin
317 ram_clkp = !ram_clkp;
318 if (write) begin
319 ram_rwds_oe = 1;
320 ram_rwds_out = 1;
321 ram_data_oe = 1;
322 ram_data_out = data[7:0];
323 data = data >> 8;
324 state = state.next;
325 end else if (ram_rwds_in) begin
326 data = data << 8;
327 data[7:0] = ram_data_in;
328 state = state.next;
329 end
330 if (state == state.first) begin
331 valid = 0;
332 if (!write) begin
333 result_valid = 1;
334 result_data = data;
335 end
336 end
337 end
338 endcase
339 end
340
341 command_ready = !valid && !result_valid;
342 end
343 end
344
345endmodule
346
347module result_printer
348 ( input bit clock
349 , input bit resetn
350
351 , output bit result_ready
352 , input bit result_valid
353 , input bit [15:0] result_data
354
355 , input bit echo_ready
356 , output bit echo_valid
357 , output bit [7:0] echo_data
358 );
359
360 bit hold_valid;
361 bit [15:0] hold;
362
363 enum
364 { DIGIT_1
365 , DIGIT_2
366 , DIGIT_3
367 , DIGIT_4
368 } state;
369
370 always @(posedge clock) begin
371 if (!resetn) begin
372 result_ready = 0;
373 echo_valid = 0;
374 echo_data = 0;
375 hold_valid = 0;
376 hold = 0;
377 state = state.first;
378 end else begin
379 if (echo_ready) echo_valid = 0;
380 if (result_ready && result_valid) begin
381 hold_valid = 1;
382 hold = result_data;
383 end
384
385 if (hold_valid && !echo_valid) begin
386 echo_valid = 1;
387 echo_data = hold[15:12];
388 hold = hold << 4;
389 if (echo_data < 10)
390 echo_data = echo_data + "0";
391 else
392 echo_data = echo_data + "A" - 10;
393 state = state.next;
394 if (state == state.first) hold_valid = 0;
395 end
396
397 result_ready = !hold_valid;
398 end
399 end
400
401endmodule
402
403module top 1module top
404 ( input bit clock 2 ( input bit clock
405 , input bit resetn 3 , input bit resetn
@@ -420,6 +18,32 @@ module top
420 bit tx_valid; 18 bit tx_valid;
421 bit [7:0] tx_data; 19 bit [7:0] tx_data;
422 20
21 bit echo_in0_ready;
22 bit echo_in0_valid;
23 bit [7:0] echo_in0_data;
24
25 bit echo_in1_ready;
26 bit echo_in1_valid;
27 bit [7:0] echo_in1_data;
28
29 bit command_ready;
30 bit command_valid;
31 bit [23:0] command_address;
32 bit command_write;
33 bit [15:0] command_data;
34
35 bit result_ready;
36 bit result_valid;
37 bit [15:0] result_data;
38
39 bit ram_rwds_oe;
40 bit ram_rwds_out;
41 assign ram_rwds = ram_rwds_oe ? ram_rwds_out : 'bZ;
42
43 bit ram_data_oe;
44 bit [7:0] ram_data_out;
45 assign ram_data = ram_data_oe ? ram_data_out : 'bZ;
46
423 alt_jtag_atlantic 47 alt_jtag_atlantic
424 #( .INSTANCE_ID(0) 48 #( .INSTANCE_ID(0)
425 , .LOG2_RXFIFO_DEPTH(6) 49 , .LOG2_RXFIFO_DEPTH(6)
@@ -438,14 +62,6 @@ module top
438 , .t_ena(rx_valid) 62 , .t_ena(rx_valid)
439 ); 63 );
440 64
441 bit echo_in0_ready;
442 bit echo_in0_valid;
443 bit [7:0] echo_in0_data;
444
445 bit echo_in1_ready;
446 bit echo_in1_valid;
447 bit [7:0] echo_in1_data;
448
449 echo_arbiter arb 65 echo_arbiter arb
450 ( .clock(clock) 66 ( .clock(clock)
451 , .resetn(resetn) 67 , .resetn(resetn)
@@ -463,12 +79,6 @@ module top
463 , .out_data(tx_data) 79 , .out_data(tx_data)
464 ); 80 );
465 81
466 bit command_ready;
467 bit command_valid;
468 bit [23:0] command_address;
469 bit command_write;
470 bit [15:0] command_data;
471
472 command_parser parser 82 command_parser parser
473 ( .clock(clock) 83 ( .clock(clock)
474 , .resetn(resetn) 84 , .resetn(resetn)
@@ -488,18 +98,6 @@ module top
488 , .command_data(command_data) 98 , .command_data(command_data)
489 ); 99 );
490 100
491 bit result_ready;
492 bit result_valid;
493 bit [15:0] result_data;
494
495 bit ram_rwds_oe;
496 bit ram_rwds_out;
497 assign ram_rwds = ram_rwds_oe ? ram_rwds_out : 'bZ;
498
499 bit ram_data_oe;
500 bit [7:0] ram_data_out;
501 assign ram_data = ram_data_oe ? ram_data_out : 'bZ;
502
503 ram_controller ram 101 ram_controller ram
504 ( .clock(clock) 102 ( .clock(clock)
505 , .resetn(resetn) 103 , .resetn(resetn)
generated by cgit v1.2.3 (git 2.51.0) at 2026-04-18 17:26:15 -0700