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-rw-r--r--tcl/init.tcl1
1 files changed, 1 insertions, 0 deletions
diff --git a/tcl/init.tcl b/tcl/init.tcl
index 2f29aec..c63734c 100644
--- a/tcl/init.tcl
+++ b/tcl/init.tcl
@@ -6,6 +6,7 @@ set_global_assignment -name TOP_LEVEL_ENTITY top
6set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 6set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
7set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1" 7set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"
8set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 8set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
9set_global_assignment -name ENABLE_SIGNALTAP OFF
9 10
10proc pin {net loc} { 11proc pin {net loc} {
11 set_location_assignment -to $net "PIN_$loc" 12 set_location_assignment -to $net "PIN_$loc"