From 3f0e2335d93038bd5a71f9de4182c6d0f818ba15 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Thu, 17 Feb 2022 08:37:06 -0800
Subject: Avoid a few warnings during build.

---
 hdl/top.sv   | 4 ++--
 tcl/init.tcl | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/hdl/top.sv b/hdl/top.sv
index d765beb..4fe4130 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -38,11 +38,11 @@ module top
 
     bit         ram_rwds_oe;
     bit         ram_rwds_out;
-    assign ram_rwds = ram_rwds_oe ? ram_rwds_out : 'bZ;
+    assign ram_rwds = ram_rwds_oe ? ram_rwds_out : 1'bZ;
 
     bit         ram_data_oe;
     bit [7:0]   ram_data_out;
-    assign ram_data = ram_data_oe ? ram_data_out : 'bZ;
+    assign ram_data = ram_data_oe ? ram_data_out : 8'bZ;
 
     alt_jtag_atlantic
         #(  .INSTANCE_ID(0)
diff --git a/tcl/init.tcl b/tcl/init.tcl
index 82a1697..103a31a 100644
--- a/tcl/init.tcl
+++ b/tcl/init.tcl
@@ -5,6 +5,7 @@ set_global_assignment -name DEVICE 10CL025YU256I7G
 set_global_assignment -name TOP_LEVEL_ENTITY top
 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"
+set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
 
 proc pin {net loc} {
     set_location_assignment -to $net "PIN_$loc"
-- 
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