From 516cc6baacf47e1c199cf0d128b6694d995859ac Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Fri, 18 Feb 2022 16:22:49 -0800
Subject: Explicitly disable signaltap compilation.

---
 tcl/init.tcl | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tcl/init.tcl b/tcl/init.tcl
index 2f29aec..c63734c 100644
--- a/tcl/init.tcl
+++ b/tcl/init.tcl
@@ -6,6 +6,7 @@ set_global_assignment -name TOP_LEVEL_ENTITY top
 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"
 set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
+set_global_assignment -name ENABLE_SIGNALTAP OFF
 
 proc pin {net loc} {
     set_location_assignment -to $net "PIN_$loc"
-- 
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