From 75410a2a7f0abb8677c1e03bfe2238923219aa46 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 20 Feb 2022 15:25:50 -0800
Subject: CSn[0] is, in fact, a lie.  We only have 23 bits of address space.

---
 hdl/command_parser.sv |  2 +-
 hdl/ram_controller.sv | 22 +++++++++++++---------
 hdl/top.sv            |  4 ++--
 tcl/init.tcl          |  3 +--
 4 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/hdl/command_parser.sv b/hdl/command_parser.sv
index 39e03db..92abced 100644
--- a/hdl/command_parser.sv
+++ b/hdl/command_parser.sv
@@ -12,7 +12,7 @@ module command_parser
 
     ,   input   bit         command_ready
     ,   output  bit         command_valid
-    ,   output  bit [23:0]  command_address
+    ,   output  bit [22:0]  command_address
     ,   output  bit         command_write
     ,   output  bit [15:0]  command_data
     );
diff --git a/hdl/ram_controller.sv b/hdl/ram_controller.sv
index 44d200b..d32560d 100644
--- a/hdl/ram_controller.sv
+++ b/hdl/ram_controller.sv
@@ -4,7 +4,7 @@ module ram_controller
 
     ,   output  bit         command_ready
     ,   input   bit         command_valid
-    ,   input   bit [23:0]  command_address
+    ,   input   bit [22:0]  command_address
     ,   input   bit         command_write
     ,   input   bit [15:0]  command_data
 
@@ -13,7 +13,7 @@ module ram_controller
     ,   output  bit [15:0]  result_data
 
     ,   output  bit         ram_resetn
-    ,   output  bit [1:0]   ram_csn
+    ,   output  bit         ram_csn
     ,   output  bit         ram_clkp
     ,   output  bit         ram_clkn
     ,   output  bit         ram_rwds_oe
@@ -27,7 +27,7 @@ module ram_controller
     assign ram_clkn = !ram_clkp;
 
     bit         valid;
-    bit [23:0]  address;
+    bit [22:0]  address;
     bit         write;
     bit [15:0]  data;
 
@@ -77,16 +77,22 @@ module ram_controller
         ,   DATA_2
         } state;
 
+    (* syn_encoding = "compact" *) enum bit
+        {   SETUP_OUTPUTS
+        ,   TOGGLE_CLOCK
+        } half_state;
+
     bit [2:0]   reset_counter;
 
+    bit         prev_rwds;
+
     always @(posedge clock) begin
         if (!resetn || reset_counter != 0) begin
             command_ready = 0;
             result_valid = 0;
             result_data = 0;
             ram_resetn = 0;
-            ram_csn[0] = 1;
-            ram_csn[1] = 1;
+            ram_csn = 1;
             ram_clkp = 0;
             ram_rwds_oe = 0;
             ram_rwds_out = 0;
@@ -117,8 +123,7 @@ module ram_controller
             end
 
             if (!valid) begin
-                ram_csn[0] = 1;
-                ram_csn[1] = 1;
+                ram_csn = 1;
                 ram_clkp = 0;
             end else begin
                 automatic bit stall = 0;
@@ -127,11 +132,10 @@ module ram_controller
 
                 CHIP_SELECT: begin
                     ram_clkp = 0; // Overriding clock to guarantee that we're starting the command with the correct clock polarity
-                    ram_csn[address[23]] = 0;
+                    ram_csn = 0;
                 end
 
                 SEND_COMMAND_1: begin
-                    ram_csn[address[23]] = 0;
                     ram_data_oe = 1;
                     ram_data_out = {!write, 1'b0, 1'b0, 5'b0}; // R/W#, ADDRSPACE, BURST, RESERVED
                 end
diff --git a/hdl/top.sv b/hdl/top.sv
index 4fe4130..e170fe0 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -3,7 +3,7 @@ module top
     ,   input   bit         resetn
 
     ,   output  bit         ram_resetn
-    ,   output  bit [1:0]   ram_csn
+    ,   output  bit         ram_csn
     ,   output  bit         ram_clkp
     ,   output  bit         ram_clkn
     ,   inout   bit         ram_rwds
@@ -28,7 +28,7 @@ module top
 
     bit         command_ready;
     bit         command_valid;
-    bit [23:0]  command_address;
+    bit [22:0]  command_address;
     bit         command_write;
     bit [15:0]  command_data;
 
diff --git a/tcl/init.tcl b/tcl/init.tcl
index c63734c..17e9c9e 100644
--- a/tcl/init.tcl
+++ b/tcl/init.tcl
@@ -72,8 +72,7 @@ rampin ram_data[4]  T10
 rampin ram_data[5]  R11
 rampin ram_data[6]  R12
 rampin ram_data[7]  R13
-rampin ram_csn[0]   N12
-rampin ram_csn[1]   P9
+rampin ram_csn      P9
 rampin ram_rwds     T14
 rampin ram_clkp     P14
 rampin ram_clkn     R14
-- 
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