From 6e39b7c16fbad9ddffc0f4eacd1799ca1b995492 Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Wed, 16 Feb 2022 12:41:28 -0800 Subject: Initial commit. --- altera/clocks.sdc | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 altera/clocks.sdc (limited to 'altera/clocks.sdc') diff --git a/altera/clocks.sdc b/altera/clocks.sdc new file mode 100644 index 0000000..c08f897 --- /dev/null +++ b/altera/clocks.sdc @@ -0,0 +1,3 @@ +# This is the clock for timing analysis, not timing-driven synthesis. +# See init.tcl for the other clock. +create_clock -period "50 MHz" clock -- cgit v1.2.3