From 5d4103339cade951363e2dc8d57e1a3e9ac1b5d7 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 20 Feb 2022 15:27:24 -0800
Subject: Fix timing and RWDS handling.

---
 hdl/ram_controller.sv | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

(limited to 'hdl')

diff --git a/hdl/ram_controller.sv b/hdl/ram_controller.sv
index d32560d..5ce0478 100644
--- a/hdl/ram_controller.sv
+++ b/hdl/ram_controller.sv
@@ -104,14 +104,13 @@ module ram_controller
             data = 0;
             slow = 0;
             state = state.first;
+            half_state = half_state.first;
             if (!resetn)
                 reset_counter = 5; // Spec wants >= 100ns of reset
             else
                 reset_counter = reset_counter - 1;
         end else begin
             ram_resetn = 1;
-            ram_rwds_oe = 0;
-            ram_data_oe = 0;
 
             if (result_ready) result_valid = 0;
             if (command_ready && command_valid) begin
@@ -123,11 +122,19 @@ module ram_controller
             end
 
             if (!valid) begin
+                ram_rwds_oe = 0;
+                ram_data_oe = 0;
                 ram_csn = 1;
                 ram_clkp = 0;
-            end else begin
+            end else if (half_state == TOGGLE_CLOCK) begin
+                half_state = half_state.next;
+                if (state != CHIP_SELECT && state != SEND_COMMAND_1)
+                    ram_clkp = !ram_clkp;
+            end else if (half_state == SETUP_OUTPUTS) begin
                 automatic bit stall = 0;
-                ram_clkp = !ram_clkp;
+                half_state = half_state.next;
+                ram_rwds_oe = 0;
+                ram_data_oe = 0;
                 case (state)
 
                 CHIP_SELECT: begin
@@ -178,13 +185,13 @@ module ram_controller
                 DATA_1, DATA_2: begin
                     if (write) begin
                         ram_rwds_oe = 1;
-                        ram_rwds_out = 1;
+                        ram_rwds_out = 0;
                         ram_data_oe = 1;
                         ram_data_out = data[7:0];
                         data = data >> 8;
-                    end else if (ram_rwds_in) begin
-                        data = data << 8;
-                        data[7:0] = ram_data_in;
+                    end else if (prev_rwds != ram_rwds_in) begin
+                        data = data >> 8;
+                        data[15:8] = ram_data_in;
                     end else begin
                         stall = 1;
                     end
@@ -204,6 +211,7 @@ module ram_controller
                 end
             end
 
+            prev_rwds = ram_rwds_in;
             command_ready = !valid && !result_valid;
         end
     end
-- 
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