From d2ecdbf5011f61228e0a3ed2441279bda551ed44 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Fri, 18 Feb 2022 16:21:52 -0800
Subject: Limit size of reset counter to something realistic.

---
 hdl/ram_controller.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'hdl')

diff --git a/hdl/ram_controller.sv b/hdl/ram_controller.sv
index 5950035..44d200b 100644
--- a/hdl/ram_controller.sv
+++ b/hdl/ram_controller.sv
@@ -77,7 +77,7 @@ module ram_controller
         ,   DATA_2
         } state;
 
-    int reset_counter;
+    bit [2:0]   reset_counter;
 
     always @(posedge clock) begin
         if (!resetn || reset_counter != 0) begin
-- 
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