Additional cleanup to make it Quartus-friendly.

1 files changed, 22 insertions, 16 deletions

diff --git a/ntoa.sv b/ntoa.sv
index f8e9f43..6da1baf 100644
--- a/ntoa.sv
+++ b/ntoa.sv
@@ -1,26 +1,32 @@
+`include "utils.svh"
+
 module ntoa
     #(  BITS = 8
     ,   BASE = 10
+    ,   BASE_BITS = $clog2(BASE)
+    ,   DIGITS = 3 // should be ceil[log(2**BITS) base BASE] which is hard to do in Verilog :-(
     )
     (   input   bit clk
     ,   input   bit reset
 
     ,   output  bit             n_ready
-    ,   input   bit             n_valid `define n_valid $past(n_valid)
-    ,   input   bit [BITS-1:0]  n_data  `define n_data $past(n_data)
+    ,   input   bit             n_valid `define n_valid `past(n_valid)
+    ,   input   bit [BITS-1:0]  n_data  `define n_data `past(n_data)
 
-    ,   input   bit         a_ready `define a_ready $past(a_ready)
+    ,   input   bit         a_ready `define a_ready `past(a_ready)
     ,   output  bit         a_valid
     ,   output  bit [7:0]   a_data
     );
 
 bit bcd_ready;
 bit bcd_valid;
-bit [b2b.DIGITS-1:0][b2b.BASE_BITS-1:0] bcd_data;
+bit [DIGITS-1:0][BASE_BITS-1:0] bcd_data;
 
 bin2bcd
     #(  .BITS(BITS)
     ,   .BASE(BASE)
+    ,   .BASE_BITS(BASE_BITS)
+    ,   .DIGITS(DIGITS)
     ) b2b
     (   .clk(clk)
     ,   .reset(reset)
@@ -30,14 +36,14 @@ bin2bcd
     ,   .bin_data(n_data)
 
     ,   .bcd_ready(bcd_ready)
-    ,   .bcd_valid(bcd_valid)   `define bcd_valid $past(bcd_valid)
-    ,   .bcd_data(bcd_data)     `define bcd_data $past(bcd_data)
+    ,   .bcd_valid(bcd_valid)   `define bcd_valid `past(bcd_valid)
+    ,   .bcd_data(bcd_data)     `define bcd_data `past(bcd_data)
     );
 
 bit bcd_b_valid;
-bit [b2b.DIGITS-1:0][b2b.BASE_BITS-1:0] bcd_b_data;
+bit [DIGITS-1:0][BASE_BITS-1:0] bcd_b_data;
 
-bit [$clog2(b2b.DIGITS):0] work;
+bit [$clog2(DIGITS):0] work;
 
 always_ff @(posedge clk) begin
     if (reset) begin
@@ -49,11 +55,11 @@ always_ff @(posedge clk) begin
             bcd_b_valid = 1;
             bcd_b_data = `bcd_data;
             // verilator lint_off WIDTH
-            work = b2b.DIGITS;
+            work = DIGITS;
             // verilator lint_on WIDTH
-            for (int i = 0; i < b2b.DIGITS - 1; ++i) begin
-                if (bcd_b_data[b2b.DIGITS-1] != 0) break;
-                bcd_b_data = { bcd_b_data[b2b.DIGITS-2:0], {b2b.BASE_BITS{1'b0}} };
+            for (int i = 0; i < DIGITS - 1; ++i) begin
+                if (bcd_b_data[DIGITS-1] != 0) break;
+                bcd_b_data = { bcd_b_data[DIGITS-2:0], {BASE_BITS{1'b0}} };
                 --work;
             end
         end
@@ -63,12 +69,12 @@ always_ff @(posedge clk) begin
             if (work != 0) begin
                 a_valid = 1;
                 // verilator lint_off WIDTH
-                if (bcd_b_data[b2b.DIGITS-1] < 10)
-                    a_data = "0" + bcd_b_data[b2b.DIGITS-1];
+                if (bcd_b_data[DIGITS-1] < 10)
+                    a_data = "0" + bcd_b_data[DIGITS-1];
                 else
-                    a_data = "a" + bcd_b_data[b2b.DIGITS-1] - 10;
+                    a_data = "a" + bcd_b_data[DIGITS-1] - 10;
                 // verilator lint_off WIDTH
-                bcd_b_data = { bcd_b_data[b2b.DIGITS-2:0], {b2b.BASE_BITS{1'b0}} };
+                bcd_b_data = { bcd_b_data[DIGITS-2:0], {BASE_BITS{1'b0}} };
                 --work;
             end else begin
                 a_valid = 1;