16 files changed, 45 insertions, 34 deletions

diff --git a/Makefile b/Makefile
index f532ce2..41fa7d9 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
-SOURCES := $(wildcard **.sv **.cpp)
-COLLATERAL := $(wildcard **.hex **.svh)
+SOURCES := $(shell find -name \*.sv -o -name \*.cpp)
+COLLATERAL := $(shell find -name \*.hex -o -name \*.svh)
 
 OPTS ?=
 
@@ -9,7 +9,7 @@ sim: build/Vtop
 
 build/Vtop: $(SOURCES) $(COLLATERAL)
         @mkdir -p build
-        verilator +1800-2017ext+sv -Wall -Wno-BLKSEQ -O3 $(OPTS) --Mdir build --trace --cc --build --exe --top-module top $(SOURCES)
+        verilator +1800-2017ext+sv -Wall -Wno-BLKSEQ -O3 -Ihdl $(OPTS) --Mdir build --trace --cc --build --exe --top-module top $(SOURCES)
 
 clean:
         rm -rf build
diff --git a/clean.bat b/clean.bat
index 6870b7a..6b31ea1 100644
--- a/clean.bat
+++ b/clean.bat
@@ -1 +1 @@
-quartus_sh -t clean.tcl

+quartus_sh -t tcl/clean.tcl

diff --git a/bin2bcd.sv b/hdl/bin2bcd.sv
index 9b1609b..9b1609b 100644
--- a/bin2bcd.sv
+++ b/hdl/bin2bcd.sv
diff --git a/fibseq.sv b/hdl/fibseq.sv
index 752c0b6..752c0b6 100644
--- a/fibseq.sv
+++ b/hdl/fibseq.sv
diff --git a/jtag_uart.sv b/hdl/jtag_uart.sv
index 5c4857d..eb0bc11 100644
--- a/jtag_uart.sv
+++ b/hdl/jtag_uart.sv
@@ -39,7 +39,7 @@ alt_jtag_atlantic
 `else
 
 bit [7:0] sim_rx_rom [0:(1<<16)-1];
-initial $readmemh("jtag_uart.hex", sim_rx_rom);
+initial $readmemh("mem/jtag_uart.hex", sim_rx_rom);
 
 bit [15:0] sim_rx_addr;
 
diff --git a/ntoa.sv b/hdl/ntoa.sv
index 6da1baf..6da1baf 100644
--- a/ntoa.sv
+++ b/hdl/ntoa.sv
diff --git a/top.sv b/hdl/top.sv
index 0244020..33c1fc5 100644
--- a/top.sv
+++ b/hdl/top.sv
@@ -15,7 +15,7 @@ bit reset;
 assign reset = !reset_n;
 
 bit [7:0] rom [0:(1<<ROM_BITS)-1];
-initial $readmemh("rom.hex", rom);
+initial $readmemh("mem/rom.hex", rom);
 
 bit [ROM_BITS-1:0] addr;
 
diff --git a/utils.svh b/hdl/utils.svh
index ddba543..ddba543 100644
--- a/utils.svh
+++ b/hdl/utils.svh
diff --git a/init.bat b/init.bat
index 526f8ea..40d352b 100644
--- a/init.bat
+++ b/init.bat
@@ -2,4 +2,4 @@ if exist toycpu.qpf (
     call clean.bat

 )

 

-quartus_sh.exe -t init.tcl

+quartus_sh.exe -t tcl/init.tcl

diff --git a/init.tcl b/init.tcl
deleted file mode 100644
index 4640ea1..0000000
--- a/init.tcl
+++ /dev/null
@@ -1,27 +0,0 @@
-project_new toycpu -revision toycpu -overwrite
-
-set_global_assignment -name DEVICE 10CL025YU256I7G
-
-set_global_assignment -name TOP_LEVEL_ENTITY top
-set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
-set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"
-
-set_location_assignment PIN_E1  -to clk
-set_location_assignment PIN_J15 -to reset_n
-
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reset_n
-
-create_base_clock -fmax "50 MHz" clk
-
-set_global_assignment -name CDF_FILE programmer.cdf
-set_global_assignment -name HEX_FILE rom.hex
-set_global_assignment -name SDC_FILE clocks.sdc
-set_global_assignment -name VERILOG_FILE bin2bcd.sv
-set_global_assignment -name VERILOG_FILE fibseq.sv
-set_global_assignment -name VERILOG_FILE jtag_uart.sv
-set_global_assignment -name VERILOG_FILE ntoa.sv
-set_global_assignment -name VERILOG_FILE top.sv
-set_global_assignment -name VERILOG_FILE utils.svh
-
-project_close
diff --git a/programmer.cdf b/jtag.cdf
index cbe240b..cbe240b 100644
--- a/programmer.cdf
+++ b/jtag.cdf
diff --git a/jtag_uart.hex b/mem/jtag_uart.hex
index 504999f..504999f 100644
--- a/jtag_uart.hex
+++ b/mem/jtag_uart.hex
diff --git a/rom.hex b/mem/rom.hex
index ee75917..ee75917 100644
--- a/rom.hex
+++ b/mem/rom.hex
diff --git a/main.cpp b/sim/main.cpp
index 3f49cb6..3f49cb6 100644
--- a/main.cpp
+++ b/sim/main.cpp
diff --git a/clean.tcl b/tcl/clean.tcl
index eeadcb7..eeadcb7 100644
--- a/clean.tcl
+++ b/tcl/clean.tcl
diff --git a/tcl/init.tcl b/tcl/init.tcl
new file mode 100644
index 0000000..7bf3a13
--- /dev/null
+++ b/tcl/init.tcl
@@ -0,0 +1,38 @@
+project_new toycpu -revision toycpu -overwrite
+
+set_global_assignment -name DEVICE 10CL025YU256I7G
+
+set_global_assignment -name TOP_LEVEL_ENTITY top
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"
+
+proc pin {loc net} {
+    set_location_assignment -to $net "PIN_$loc"
+    set_instance_assignment -name IO_STANDARD "3.3V LVTTL" -to $net
+}
+
+pin E1  clk
+pin J15 reset_n
+
+create_base_clock -fmax "50 MHz" clk
+
+proc add_files {typ ext dir} {
+    foreach name [glob -nocomplain -directory $dir -type f "*.$ext"] {
+        set_global_assignment -name "${typ}_FILE" $name
+    }
+}
+
+proc add_dir {dir} {
+    add_files CDF cdf $dir
+    add_files HEX hex $dir
+    add_files SDC sdc $dir
+    add_files VERILOG sv $dir
+
+    foreach subdir [glob -nocomplain -directory $dir -type d *] {
+        add_dir $subdir
+    }
+}
+
+add_dir "."
+
+project_close