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-rw-r--r--altera/clocks.sdc2
1 files changed, 2 insertions, 0 deletions
diff --git a/altera/clocks.sdc b/altera/clocks.sdc
index f613011..239c91a 100644
--- a/altera/clocks.sdc
+++ b/altera/clocks.sdc
@@ -1 +1,3 @@
1# This is the clock for timing analysis, not timing-driven synthesis.
2# See init.tcl for the other clock.
1create_clock -period "50 MHz" clk 3create_clock -period "50 MHz" clk