1 files changed, 0 insertions, 152 deletions
diff --git a/top.sv b/top.sv
deleted file mode 100644
index 0244020..0000000
--- a/top.sv
+++ /dev/null
@@ -1,152 +0,0 @@
-`include "utils.svh"
-module top
-    #(  FIB_BITS = 16
-    ,   FIB_BASE = 10
-    ,   FIB_DIGITS = 5
-    ,   ROM_BITS = 8
-    )
-    (   input   bit clk     // verilator public
-    ,   input   bit reset_n // verilator public
-    );
-bit reset;
-assign reset = !reset_n;
-bit [7:0] rom [0:(1<<ROM_BITS)-1];
-initial $readmemh("rom.hex", rom);
-bit [ROM_BITS-1:0] addr;
-bit rx_ready;
-bit rx_valid;
-bit [7:0] rx_data;
-bit tx_ready;
-bit tx_valid;
-bit [7:0] tx_data;
-jtag_uart
-    #(  .INSTANCE(0)
-    ) uart0
-    (   .clk(clk)
-    ,   .reset(reset)
-    ,   .rx_ready(rx_ready)
-    ,   .rx_valid(rx_valid) `define rx_valid `past(rx_valid)
-    ,   .rx_data(rx_data)   `define rx_data `past(rx_data)
-    ,   .tx_ready(tx_ready) `define tx_ready `past(tx_ready)
-    ,   .tx_valid(tx_valid)
-    ,   .tx_data(tx_data)
-    );
-bit fib_ready;
-bit fib_valid;
-bit [FIB_BITS-1:0] fib_data;
-fibseq
-    #(  .BITS(FIB_BITS)
-    ) fib
-    (   .clk(clk)
-    ,   .reset(reset)
-    ,   .ready(fib_ready)
-    ,   .valid(fib_valid)
-    ,   .data(fib_data)
-    );
-bit fib_a_ready;
-bit fib_a_valid;
-bit [7:0] fib_a_data;
-ntoa
-    #(  .BITS(FIB_BITS)
-    ,   .BASE(FIB_BASE)
-    ,   .DIGITS(FIB_DIGITS)
-    ) fib_ntoa
-    (   .clk(clk)
-    ,   .reset(reset)
-    ,   .n_ready(fib_ready)
-    ,   .n_valid(fib_valid)
-    ,   .n_data(fib_data)
-    ,   .a_ready(fib_a_ready)
-    ,   .a_valid(fib_a_valid)   `define fib_a_valid `past(fib_a_valid)
-    ,   .a_data(fib_a_data)     `define fib_a_data `past(fib_a_data)
-    );
-enum
-    {   INTRO_ECHO
-    ,   ECHO
-    ,   INTRO_FIB
-    ,   FIB
-    } state;
-bit tmp_valid;
-bit [7:0] tmp_data;
-always_ff @(posedge clk) begin
-    if (reset) begin
-        addr = 0;
-        rx_ready = 0;
-        tx_valid = 0;
-        fib_a_ready = 0;
-        state = state.first;
-        tmp_valid = 0;
-    end else case (state)
-        INTRO_ECHO, INTRO_FIB: begin
-            automatic bit [7:0] data = rom[addr];
-            if (`tx_ready) tx_valid = 0;
-            if (!tx_valid && (data != 0)) begin
-                tx_valid = 1;
-                tx_data = data;
-                ++addr;
-            end else if (data == 0) begin
-                ++addr;
-                state = state.next;
-            end
-        end
-        ECHO: begin
-            if (`tx_ready && tx_valid && tx_data == "\n") begin
-                // FIXME race; we aren't going to consume input this cycle, but we might have tmp_valid or rx_ready asserted
-                rx_ready = 0;
-                tx_valid = 0;
-                state = INTRO_FIB;
-            end else begin
-                if (`tx_ready) tx_valid = 0;
-                if (rx_ready && `rx_valid) begin
-                    tmp_valid = 1;
-                    tmp_data = `rx_data;
-                end
-                if (!tx_valid && tmp_valid) begin
-                    tx_valid = 1;
-                    tx_data = tmp_data;
-                    tmp_valid = 0;
-                end
-                rx_ready = !tmp_valid;
-            end
-        end
-        FIB: begin
-            if (`tx_ready) tx_valid = 0;
-            if (fib_a_ready && `fib_a_valid) begin
-                tmp_valid = 1;
-                tmp_data = `fib_a_data;
-            end
-            if (!tx_valid && tmp_valid) begin
-                tx_valid = 1;
-                tx_data = tmp_data;
-                tmp_valid = 0;
-            end
-            fib_a_ready = !tmp_valid;
-        end
-    endcase
-end
-endmodule

diff --git a/top.sv b/top.sv deleted file mode 100644 index 0244020..0000000 --- a/top.sv +++ /dev/null
@@ -1,152 +0,0 @@
1	`include "utils.svh"
2
3	module top
4	#( FIB_BITS = 16
5	, FIB_BASE = 10
6	, FIB_DIGITS = 5
7
8	, ROM_BITS = 8
9	)
10	( input bit clk // verilator public
11	, input bit reset_n // verilator public
12	);
13
14	bit reset;
15	assign reset = !reset_n;
16
17	bit [7:0] rom [0:(1<<ROM_BITS)-1];
18	initial $readmemh("rom.hex", rom);
19
20	bit [ROM_BITS-1:0] addr;
21
22	bit rx_ready;
23	bit rx_valid;
24	bit [7:0] rx_data;
25
26	bit tx_ready;
27	bit tx_valid;
28	bit [7:0] tx_data;
29
30	jtag_uart
31	#( .INSTANCE(0)
32	) uart0
33	( .clk(clk)
34	, .reset(reset)
35
36	, .rx_ready(rx_ready)
37	, .rx_valid(rx_valid) `define rx_valid `past(rx_valid)
38	, .rx_data(rx_data) `define rx_data `past(rx_data)
39
40	, .tx_ready(tx_ready) `define tx_ready `past(tx_ready)
41	, .tx_valid(tx_valid)
42	, .tx_data(tx_data)
43	);
44
45	bit fib_ready;
46	bit fib_valid;
47	bit [FIB_BITS-1:0] fib_data;
48
49	fibseq
50	#( .BITS(FIB_BITS)
51	) fib
52	( .clk(clk)
53	, .reset(reset)
54
55	, .ready(fib_ready)
56	, .valid(fib_valid)
57	, .data(fib_data)
58	);
59
60	bit fib_a_ready;
61	bit fib_a_valid;
62	bit [7:0] fib_a_data;
63
64	ntoa
65	#( .BITS(FIB_BITS)
66	, .BASE(FIB_BASE)
67	, .DIGITS(FIB_DIGITS)
68	) fib_ntoa
69	( .clk(clk)
70	, .reset(reset)
71
72	, .n_ready(fib_ready)
73	, .n_valid(fib_valid)
74	, .n_data(fib_data)
75
76	, .a_ready(fib_a_ready)
77	, .a_valid(fib_a_valid) `define fib_a_valid `past(fib_a_valid)
78	, .a_data(fib_a_data) `define fib_a_data `past(fib_a_data)
79	);
80
81	enum
82	{ INTRO_ECHO
83	, ECHO
84	, INTRO_FIB
85	, FIB
86	} state;
87
88	bit tmp_valid;
89	bit [7:0] tmp_data;
90
91	always_ff @(posedge clk) begin
92	if (reset) begin
93	addr = 0;
94	rx_ready = 0;
95	tx_valid = 0;
96	fib_a_ready = 0;
97	state = state.first;
98	tmp_valid = 0;
99	end else case (state)
100
101	INTRO_ECHO, INTRO_FIB: begin
102	automatic bit [7:0] data = rom[addr];
103	if (`tx_ready) tx_valid = 0;
104	if (!tx_valid && (data != 0)) begin
105	tx_valid = 1;
106	tx_data = data;
107	++addr;
108	end else if (data == 0) begin
109	++addr;
110	state = state.next;
111	end
112	end
113
114	ECHO: begin
115	if (`tx_ready && tx_valid && tx_data == "\n") begin
116	// FIXME race; we aren't going to consume input this cycle, but we might have tmp_valid or rx_ready asserted
117	rx_ready = 0;
118	tx_valid = 0;
119	state = INTRO_FIB;
120	end else begin
121	if (`tx_ready) tx_valid = 0;
122	if (rx_ready && `rx_valid) begin
123	tmp_valid = 1;
124	tmp_data = `rx_data;
125	end
126	if (!tx_valid && tmp_valid) begin
127	tx_valid = 1;
128	tx_data = tmp_data;
129	tmp_valid = 0;
130	end
131	rx_ready = !tmp_valid;
132	end
133	end
134
135	FIB: begin
136	if (`tx_ready) tx_valid = 0;
137	if (fib_a_ready && `fib_a_valid) begin
138	tmp_valid = 1;
139	tmp_data = `fib_a_data;
140	end
141	if (!tx_valid && tmp_valid) begin
142	tx_valid = 1;
143	tx_data = tmp_data;
144	tmp_valid = 0;
145	end
146	fib_a_ready = !tmp_valid;
147	end
148
149	endcase
150	end
151
152	endmodule