From 8056863ce3e95db52e027a0f0babe51df1cb9a4e Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Tue, 23 Mar 2021 21:52:41 -0700 Subject: Additional cleanup to make it Quartus-friendly. --- bin2bcd.sv | 13 +++++++------ fibseq.sv | 4 +++- init.tcl | 1 + jtag_uart.sv | 8 +++++--- ntoa.sv | 38 ++++++++++++++++++++++---------------- top.sv | 17 +++++++++++------ utils.svh | 5 +++++ 7 files changed, 54 insertions(+), 32 deletions(-) create mode 100644 utils.svh diff --git a/bin2bcd.sv b/bin2bcd.sv index 5e2dbd3..9b1609b 100644 --- a/bin2bcd.sv +++ b/bin2bcd.sv @@ -1,23 +1,24 @@ +`include "utils.svh" + module bin2bcd #( BITS = 8 , BASE = 10 + , BASE_BITS = $clog2(BASE) + , DIGITS = 3 // should be ceil[log(2**BITS) base BASE] which is hard to do in Verilog :-( , MAX_SKIP = BITS ) ( input bit clk , input bit reset , output bit bin_ready - , input bit bin_valid `define bin_valid $past(bin_valid) - , input bit [BITS-1:0] bin_data `define bin_data $past(bin_data) + , input bit bin_valid `define bin_valid `past(bin_valid) + , input bit [BITS-1:0] bin_data `define bin_data `past(bin_data) - , input bit bcd_ready `define bcd_ready $past(bcd_ready) + , input bit bcd_ready `define bcd_ready `past(bcd_ready) , output bit bcd_valid , output bit [DIGITS-1:0][BASE_BITS-1:0] bcd_data ); -localparam BASE_BITS = $clog2(BASE); -localparam DIGITS = $rtoi($ceil($ln(1 << BITS) / $ln(BASE))); - bit bin_b_valid; bit [BITS-1:0] bin_b_data; diff --git a/fibseq.sv b/fibseq.sv index f877b98..752c0b6 100644 --- a/fibseq.sv +++ b/fibseq.sv @@ -1,10 +1,12 @@ +`include "utils.svh" + module fibseq #( BITS = 8 ) ( input bit clk , input bit reset - , input bit ready `define ready $past(ready) + , input bit ready `define ready `past(ready) , output bit valid , output bit [BITS-1:0] data ); diff --git a/init.tcl b/init.tcl index 33897e5..4640ea1 100644 --- a/init.tcl +++ b/init.tcl @@ -22,5 +22,6 @@ set_global_assignment -name VERILOG_FILE fibseq.sv set_global_assignment -name VERILOG_FILE jtag_uart.sv set_global_assignment -name VERILOG_FILE ntoa.sv set_global_assignment -name VERILOG_FILE top.sv +set_global_assignment -name VERILOG_FILE utils.svh project_close diff --git a/jtag_uart.sv b/jtag_uart.sv index ddb5ecb..5c4857d 100644 --- a/jtag_uart.sv +++ b/jtag_uart.sv @@ -1,3 +1,5 @@ +`include "utils.svh" + module jtag_uart #( INSTANCE = 0 @@ -7,13 +9,13 @@ module jtag_uart ( input bit clk , input bit reset - , input bit rx_ready `define rx_ready $past(rx_ready) + , input bit rx_ready `define rx_ready `past(rx_ready) , output bit rx_valid , output bit [7:0] rx_data , output bit tx_ready - , input bit tx_valid `define tx_valid $past(tx_valid) - , input bit [7:0] tx_data `define tx_data $past(tx_data) + , input bit tx_valid `define tx_valid `past(tx_valid) + , input bit [7:0] tx_data `define tx_data `past(tx_data) ); `ifdef SYNTHESIS diff --git a/ntoa.sv b/ntoa.sv index f8e9f43..6da1baf 100644 --- a/ntoa.sv +++ b/ntoa.sv @@ -1,26 +1,32 @@ +`include "utils.svh" + module ntoa #( BITS = 8 , BASE = 10 + , BASE_BITS = $clog2(BASE) + , DIGITS = 3 // should be ceil[log(2**BITS) base BASE] which is hard to do in Verilog :-( ) ( input bit clk , input bit reset , output bit n_ready - , input bit n_valid `define n_valid $past(n_valid) - , input bit [BITS-1:0] n_data `define n_data $past(n_data) + , input bit n_valid `define n_valid `past(n_valid) + , input bit [BITS-1:0] n_data `define n_data `past(n_data) - , input bit a_ready `define a_ready $past(a_ready) + , input bit a_ready `define a_ready `past(a_ready) , output bit a_valid , output bit [7:0] a_data ); bit bcd_ready; bit bcd_valid; -bit [b2b.DIGITS-1:0][b2b.BASE_BITS-1:0] bcd_data; +bit [DIGITS-1:0][BASE_BITS-1:0] bcd_data; bin2bcd #( .BITS(BITS) , .BASE(BASE) + , .BASE_BITS(BASE_BITS) + , .DIGITS(DIGITS) ) b2b ( .clk(clk) , .reset(reset) @@ -30,14 +36,14 @@ bin2bcd , .bin_data(n_data) , .bcd_ready(bcd_ready) - , .bcd_valid(bcd_valid) `define bcd_valid $past(bcd_valid) - , .bcd_data(bcd_data) `define bcd_data $past(bcd_data) + , .bcd_valid(bcd_valid) `define bcd_valid `past(bcd_valid) + , .bcd_data(bcd_data) `define bcd_data `past(bcd_data) ); bit bcd_b_valid; -bit [b2b.DIGITS-1:0][b2b.BASE_BITS-1:0] bcd_b_data; +bit [DIGITS-1:0][BASE_BITS-1:0] bcd_b_data; -bit [$clog2(b2b.DIGITS):0] work; +bit [$clog2(DIGITS):0] work; always_ff @(posedge clk) begin if (reset) begin @@ -49,11 +55,11 @@ always_ff @(posedge clk) begin bcd_b_valid = 1; bcd_b_data = `bcd_data; // verilator lint_off WIDTH - work = b2b.DIGITS; + work = DIGITS; // verilator lint_on WIDTH - for (int i = 0; i < b2b.DIGITS - 1; ++i) begin - if (bcd_b_data[b2b.DIGITS-1] != 0) break; - bcd_b_data = { bcd_b_data[b2b.DIGITS-2:0], {b2b.BASE_BITS{1'b0}} }; + for (int i = 0; i < DIGITS - 1; ++i) begin + if (bcd_b_data[DIGITS-1] != 0) break; + bcd_b_data = { bcd_b_data[DIGITS-2:0], {BASE_BITS{1'b0}} }; --work; end end @@ -63,12 +69,12 @@ always_ff @(posedge clk) begin if (work != 0) begin a_valid = 1; // verilator lint_off WIDTH - if (bcd_b_data[b2b.DIGITS-1] < 10) - a_data = "0" + bcd_b_data[b2b.DIGITS-1]; + if (bcd_b_data[DIGITS-1] < 10) + a_data = "0" + bcd_b_data[DIGITS-1]; else - a_data = "a" + bcd_b_data[b2b.DIGITS-1] - 10; + a_data = "a" + bcd_b_data[DIGITS-1] - 10; // verilator lint_off WIDTH - bcd_b_data = { bcd_b_data[b2b.DIGITS-2:0], {b2b.BASE_BITS{1'b0}} }; + bcd_b_data = { bcd_b_data[DIGITS-2:0], {BASE_BITS{1'b0}} }; --work; end else begin a_valid = 1; diff --git a/top.sv b/top.sv index cbb5b55..0244020 100644 --- a/top.sv +++ b/top.sv @@ -1,6 +1,10 @@ +`include "utils.svh" + module top #( FIB_BITS = 16 , FIB_BASE = 10 + , FIB_DIGITS = 5 + , ROM_BITS = 8 ) ( input bit clk // verilator public @@ -30,10 +34,10 @@ jtag_uart , .reset(reset) , .rx_ready(rx_ready) - , .rx_valid(rx_valid) `define rx_valid $past(rx_valid) - , .rx_data(rx_data) `define rx_data $past(rx_data) + , .rx_valid(rx_valid) `define rx_valid `past(rx_valid) + , .rx_data(rx_data) `define rx_data `past(rx_data) - , .tx_ready(tx_ready) `define tx_ready $past(tx_ready) + , .tx_ready(tx_ready) `define tx_ready `past(tx_ready) , .tx_valid(tx_valid) , .tx_data(tx_data) ); @@ -60,6 +64,7 @@ bit [7:0] fib_a_data; ntoa #( .BITS(FIB_BITS) , .BASE(FIB_BASE) + , .DIGITS(FIB_DIGITS) ) fib_ntoa ( .clk(clk) , .reset(reset) @@ -69,8 +74,8 @@ ntoa , .n_data(fib_data) , .a_ready(fib_a_ready) - , .a_valid(fib_a_valid) `define fib_a_valid $past(fib_a_valid) - , .a_data(fib_a_data) `define fib_a_data $past(fib_a_data) + , .a_valid(fib_a_valid) `define fib_a_valid `past(fib_a_valid) + , .a_data(fib_a_data) `define fib_a_data `past(fib_a_data) ); enum @@ -91,7 +96,7 @@ always_ff @(posedge clk) begin fib_a_ready = 0; state = state.first; tmp_valid = 0; - end else unique0 case (state) + end else case (state) INTRO_ECHO, INTRO_FIB: begin automatic bit [7:0] data = rom[addr]; diff --git a/utils.svh b/utils.svh new file mode 100644 index 0000000..ddba543 --- /dev/null +++ b/utils.svh @@ -0,0 +1,5 @@ +`ifdef SYNTHESIS +`define past(x) x +`else +`define past(x) $past(x) +`endif -- cgit v1.2.3