From 93a4ad185a48e8f2da76cc62fca8160ba4c960a6 Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Sun, 28 Mar 2021 14:03:50 -0700 Subject: Trivial changes from actually testing at Ducky office. --- altera/clocks.sdc | 2 ++ altera/jtag.cdf | 5 ++--- hdl/top.sv | 6 ++++-- tcl/init.tcl | 2 ++ 4 files changed, 10 insertions(+), 5 deletions(-) diff --git a/altera/clocks.sdc b/altera/clocks.sdc index f613011..239c91a 100644 --- a/altera/clocks.sdc +++ b/altera/clocks.sdc @@ -1 +1,3 @@ +# This is the clock for timing analysis, not timing-driven synthesis. +# See init.tcl for the other clock. create_clock -period "50 MHz" clk diff --git a/altera/jtag.cdf b/altera/jtag.cdf index cbe240b..ac80090 100644 --- a/altera/jtag.cdf +++ b/altera/jtag.cdf @@ -1,10 +1,9 @@ -/* XXX Copy this from a working setup on Ducky hardware */ JedecChain; FileRevision(JESD32A); DefaultMfr(6E); - P ActionCode(Cfg) - Device PartName(10CL025YU256) Path("C:/Users/mike/Desktop/toycpu/") File("toycpu.pof") MfrSpec(OpMask(1)); + P ActionCode(Ign) + Device PartName(10CL025Y) MfrSpec(OpMask(0)); ChainEnd; diff --git a/hdl/top.sv b/hdl/top.sv index c2f56bc..41b3e23 100644 --- a/hdl/top.sv +++ b/hdl/top.sv @@ -11,8 +11,10 @@ module top , input bit reset_n // verilator public ); -bit reset; -assign reset = !reset_n; +bit reset = 0; +bit have_reset = 0; +always_ff @(posedge clk) if (reset) have_reset <= 1; +assign reset = !reset_n || !have_reset; bit [7:0] rom [0:(1<