From 93a4ad185a48e8f2da76cc62fca8160ba4c960a6 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 28 Mar 2021 14:03:50 -0700
Subject: Trivial changes from actually testing at Ducky office.

---
 altera/clocks.sdc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'altera/clocks.sdc')

diff --git a/altera/clocks.sdc b/altera/clocks.sdc
index f613011..239c91a 100644
--- a/altera/clocks.sdc
+++ b/altera/clocks.sdc
@@ -1 +1,3 @@
+# This is the clock for timing analysis, not timing-driven synthesis.
+# See init.tcl for the other clock.
 create_clock -period "50 MHz" clk
-- 
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