From 0f95f3efbe4879bcf8b24aafda1c10dd95e9dd40 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Tue, 23 Mar 2021 19:01:29 -0700
Subject: Replace dibble dabble algorithm with variant that tests after the
 add.

This makes it really easy to support odd bases.
---
 bin2bcd.sv | 52 ++++++++++++++--------------------------------------
 1 file changed, 14 insertions(+), 38 deletions(-)

(limited to 'bin2bcd.sv')

diff --git a/bin2bcd.sv b/bin2bcd.sv
index 266860c..8e618c6 100644
--- a/bin2bcd.sv
+++ b/bin2bcd.sv
@@ -15,37 +15,8 @@ module bin2bcd
     ,   output  bit [DIGITS-1:0][BASE_BITS-1:0] bcd_data
     );
 
-// FIXME I don't think this works for odd bases
-
 localparam BASE_BITS = $clog2(BASE);
-localparam SLACK = (1 << BASE_BITS) - BASE;
 localparam DIGITS = $rtoi($ceil($ln(1 << BITS) / $ln(BASE)));
-localparam CARRY_TEST = $rtoi($ceil($itor(BASE) / 2));
-localparam CARRY_ADD = $rtoi($ceil($itor(SLACK) / 2));
-
-`ifdef DEBUG_BIN2BCD
-
-initial $display("%d BITS", BITS);
-initial $display("%d BASE", BASE);
-initial $display("%d BASE_BITS", BASE_BITS);
-initial $display("%d SLACK", SLACK);
-initial $display("%d DIGITS", DIGITS);
-initial $display("%d CARRY_TEST", CARRY_TEST);
-initial $display("%d CARRY_ADD", CARRY_ADD);
-
-initial for(int i = 0; i < BASE; i = i + 1) begin
-    // verilator lint_off WIDTH
-    automatic bit [BASE_BITS-1:0] n = i;
-    automatic bit [BASE_BITS-1:0] a = n >= CARRY_TEST ? CARRY_ADD : 0;
-    automatic bit [BASE_BITS-1:0] s = n + a;
-    // verilator lint_on WIDTH
-    automatic bit c;
-    automatic bit [BASE_BITS-1:0] d;
-    {c, d} = {s, 1'b0};
-    $display("\t\t(%x + %x => %x) * 2 => %x:%x", n, a, s, c, d);
-end
-
-`endif
 
 bit bin_b_valid;
 bit [BITS-1:0] bin_b_data;
@@ -65,7 +36,7 @@ always_ff @(posedge clk) begin
             bin_b_data = `bin_data;
             bcd = 0;
             work = BITS;
-            for (int i = 0; i < BITS && i < MAX_SKIP; i = i + 1) begin
+            for (int i = 0; i < BITS && i < MAX_SKIP; ++i) begin
                 if (bin_b_data[BITS-1]) break;
                 bin_b_data = { bin_b_data[BITS-2:0], 1'b0 };
                 work = work - 1;
@@ -73,14 +44,19 @@ always_ff @(posedge clk) begin
         end
 
         if (bin_b_valid && work != 0) begin
-            for (int i = 0; i < DIGITS; i = i + 1)
-                // verilator lint_off WIDTH
-                if (bcd[i] >= CARRY_TEST) bcd[i] = bcd[i] + CARRY_ADD;
-                // verilator lint_on WIDTH
-            for (int i = DIGITS - 1; i > 0; i = i - 1)
-                bcd[i] = { bcd[i][BASE_BITS-2:0], bcd[i-1][BASE_BITS-1] };
-            bcd[0] = { bcd[0][BASE_BITS-2:0], bin_b_data[BITS-1] };
-            bin_b_data = { bin_b_data[BITS-2:0], 1'b0 };
+            automatic bit carry = bin_b_data[BITS-1];
+            for (int i = 0; i < DIGITS; ++i) begin
+                {carry, bcd[i]} = {bcd[i], carry};
+                if ({carry, bcd[i]} >= BASE) begin
+                    // verilator lint_off WIDTH
+                    bcd[i] = {carry, bcd[i]} - BASE;
+                    // verilator lint_on WIDTH
+                    carry = 1;
+                end
+            end
+            assert(!carry);
+
+            bin_b_data = bin_b_data << 1;
 
             work = work - 1;
         end
-- 
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