From 5c1df6d27f5dac143efc9ce84689b863dbee45bd Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Wed, 24 Mar 2021 08:35:07 -0700
Subject: Reorganize repo layout to make it a little easier to work within.

---
 bin2bcd.sv | 76 --------------------------------------------------------------
 1 file changed, 76 deletions(-)
 delete mode 100644 bin2bcd.sv

(limited to 'bin2bcd.sv')

diff --git a/bin2bcd.sv b/bin2bcd.sv
deleted file mode 100644
index 9b1609b..0000000
--- a/bin2bcd.sv
+++ /dev/null
@@ -1,76 +0,0 @@
-`include "utils.svh"
-
-module bin2bcd
-    #(  BITS = 8
-    ,   BASE = 10
-    ,   BASE_BITS = $clog2(BASE)
-    ,   DIGITS = 3 // should be ceil[log(2**BITS) base BASE] which is hard to do in Verilog :-(
-    ,   MAX_SKIP = BITS
-    )
-    (   input   bit clk
-    ,   input   bit reset
-
-    ,   output  bit             bin_ready
-    ,   input   bit             bin_valid   `define bin_valid `past(bin_valid)
-    ,   input   bit [BITS-1:0]  bin_data    `define bin_data `past(bin_data)
-
-    ,   input   bit                             bcd_ready   `define bcd_ready `past(bcd_ready)
-    ,   output  bit                             bcd_valid
-    ,   output  bit [DIGITS-1:0][BASE_BITS-1:0] bcd_data
-    );
-
-bit bin_b_valid;
-bit [BITS-1:0] bin_b_data;
-
-bit [DIGITS-1:0][BASE_BITS-1:0] bcd;
-
-bit [$clog2(BITS):0] work;
-
-always_ff @(posedge clk) begin
-    if (reset) begin
-        bin_ready = 0;
-        bcd_valid = 0;
-        bin_b_valid = 0;
-    end else begin
-        if (bin_ready && `bin_valid) begin
-            bin_b_valid = 1;
-            bin_b_data = `bin_data;
-            bcd = 0;
-            work = BITS;
-            for (int i = 0; i < BITS && i < MAX_SKIP; ++i) begin
-                if (bin_b_data[BITS-1]) break;
-                bin_b_data = { bin_b_data[BITS-2:0], 1'b0 };
-                work = work - 1;
-            end
-        end
-
-        if (bin_b_valid && work != 0) begin
-            automatic bit carry = bin_b_data[BITS-1];
-            for (int i = 0; i < DIGITS; ++i) begin
-                {carry, bcd[i]} = {bcd[i], carry};
-                if ({carry, bcd[i]} >= BASE) begin
-                    // verilator lint_off WIDTH
-                    bcd[i] = {carry, bcd[i]} - BASE;
-                    // verilator lint_on WIDTH
-                    carry = 1;
-                end
-            end
-            assert(!carry);
-
-            bin_b_data = bin_b_data << 1;
-
-            work = work - 1;
-        end
-
-        if (`bcd_ready) bcd_valid = 0;
-        if (!bcd_valid && bin_b_valid && work == 0) begin
-            bcd_valid = 1;
-            bcd_data = bcd;
-            bin_b_valid = 0;
-        end
-
-        bin_ready = !bin_b_valid;
-    end
-end
-
-endmodule
-- 
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