`include "util.svh"

module fibseq
    #(  BITS = 8
    )
    (   input   bit clk
    ,   input   bit reset

    ,   input   bit             ready   `define ready `past(ready)
    ,   output  bit             valid
    ,   output  bit [BITS-1:0]  data
    );

bit [BITS-1:0] a;
bit [BITS-1:0] b;

always_ff @(posedge clk) begin
    if (reset) begin
        valid = 0;
        a = 0;
        b = 1;
    end else begin
        if (`ready) valid = 0;
        if (!valid) begin
            valid = 1;
            data = a;
            {a, b} = {b, a + b};
        end
    end
end

endmodule